EP0175748A1 - Parallel synchronous operation. - Google Patents

Parallel synchronous operation.

Info

Publication number
EP0175748A1
EP0175748A1 EP85901643A EP85901643A EP0175748A1 EP 0175748 A1 EP0175748 A1 EP 0175748A1 EP 85901643 A EP85901643 A EP 85901643A EP 85901643 A EP85901643 A EP 85901643A EP 0175748 A1 EP0175748 A1 EP 0175748A1
Authority
EP
European Patent Office
Prior art keywords
clock
switch
circuit
flipflop
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85901643A
Other languages
German (de)
French (fr)
Other versions
EP0175748B1 (en
Inventor
Goesta Ingvar Sundell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to AT85901643T priority Critical patent/ATE42845T1/en
Publication of EP0175748A1 publication Critical patent/EP0175748A1/en
Application granted granted Critical
Publication of EP0175748B1 publication Critical patent/EP0175748B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level

Definitions

  • the invention relates to apparatus for providing parallel synchronous operation of at least two micro-processors, in a computer system.
  • Modern computers and computer systems often include micro-processors, with which sub-functions are performed. To obtain great reliability in their perfor- mance it is desirable simultaneously to perform the subfunctions in two microprocessors working in parallel. They must operate synchronous to enable comparison of their results. Their clock frequency is controlled by the computer system clock, which has its frequency divided in the clock counters of the microprocessors. There is often a fixed division by a factor of four. If further division is required this is suitably performed with the aid of a JK-flipflop connected to the respective clock input.
  • a problem in synchronizing two or more microprocessors is that their internal functions are inaccessible from outside. It is therefore not possible to achieve parallel synchronism with the aid of a resetting pulse.
  • the present invention relates to apparatus, with the aid of which two or more mircroprocessors are brought into parallel synchronous operation.
  • the invention is characterized in the accompanying claims.
  • Figure 1 illustrates one embodiment of the invention and Figure 2 another embodiment.
  • Figure 3 is a time chart for the signals with respect to synchronization.
  • Figure 1 is a logic diagram where the apparatus comprises a negative exclusive OR circuit 3 and an AND circuit 4 connected to two clock counters 1,2, each associated with a microprocessor 6,7.
  • the computer system clock Cl is connected to the input of the clock counter 1.
  • the output of the circuit 4 is connected to the input of the other clock counter 2, one input of the circuit 4 being connected to the system clock Cl.
  • the frequency of this clock is divided by a factor of four in the clock counters 1,2.
  • the outputs of the latter are each connected to an input of the circuit 3, the output of which is connected to the other input of the circuit 4.
  • the output of the circuit 3 will be zero for a signal difference at the outputs of the clock counters 1,2.
  • the system clock signal is then prevented by the circuit 4 from reaching the clock counter 2. If there is no difference in the signals on the outputs of the clock counters, the output of the circuit 3 is ONE, and the circuit 4 allows the system clock signals to reach the clock counter 2. From this it follows that for asynchronism between the clock counters, the counter 2 will be periodcally stopped until parallel synchronism occurs (described in detail in connection with Figure 3).
  • FIG. 2 illustrates another embodiment.
  • An arithmetic circuit 5 comprising a JK-flipflop to each microprocessor is connected between the system clock and the microprocessors.
  • the arithmetic circuit divides the system clock frequency by a factor of two, resulting in that the total division of the frequency will be by a factor of eight.
  • the JK inputs to the flipflop having its output connected to the clock input of the other microprocessor 2 are commonly connected to the output of the logical circuit 3.
  • the AND function of the circuit 4 in Figure 1 is thus replaced.
  • the time chart in Figure 3 illustrates the phasing-in to parallel synchronism between the mircoprocessors, in the case where the frequency of the signal clock Cl is divided by a factor of eight, according to Figure 2.
  • A, , B, and C-. depict the frequecy division sequence in the microprocessor 1
  • a « B « and C Constant depict the frequency division sequence in the microprocessor 2.
  • One of the two most unfavourable cases possible is illustrated in the diagram.
  • a positive period is denoted by a logical ONE and a negative by a logical ZERO.
  • B shifts when A goes from 1 to O
  • C shifts when B goes from 1 to O.
  • the Cl pulses to A 2 are stopped at difference between C, and m. According to the chart, this occurs for the first time when C, goes from O to 1 after the Cl period 3. A 2 is in the state 1 until the Cl period when C, has gone from 1 to 0, i.e. after the period 8. Then A relie gets the Cl pulse and goes from 1 to 0. At the same time B « goes from 1 to 0 and C 2 from 0 to 1. Then there is once again a difference between C, and C 2 , thus A 2 being blocked again for the Cl pulses. This difference prevails until C-, once again goes from 0 to 1, which takes place after the period 11. There is subsequent equality between A, and A 2 , B-. and B 2 , C, and C 2 , i.e.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Soil Working Implements (AREA)
  • Moving Of Heads (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
  • Enzymes And Modification Thereof (AREA)
  • Medicines Containing Material From Animals Or Micro-Organisms (AREA)
  • Manufacturing Of Steel Electrode Plates (AREA)
  • Valve Device For Special Equipments (AREA)
  • Selective Calling Equipment (AREA)
  • Control Of Eletrric Generators (AREA)
  • Dram (AREA)
  • Image Processing (AREA)
  • Control Of Multiple Motors (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Mechanical Coupling Of Light Guides (AREA)
  • Basic Packing Technique (AREA)
  • Manipulation Of Pulses (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)

Abstract

En vue d'un fonctionnement synchrone parallèle entre deux microprocesseurs (1, 2), on prévoit un commutateur (4) commandé par un circuit logique (3), qui détecte les sorties d'horloge des microprocesseurs. S'il y a déviation du synchronisme, le circuit logique (3) envoie un signal au commutateur (4) qui interrompt alors le signal d'horloge arrivant à l'entrée d'horloge d'un microprocesseur (2) si bien qu'un synchronisme parallèle est obtenu par étapes.For a synchronous parallel operation between two microprocessors (1, 2), there is provided a switch (4) controlled by a logic circuit (3), which detects the clock outputs of the microprocessors. If there is a deviation from the synchronism, the logic circuit (3) sends a signal to the switch (4) which then interrupts the clock signal arriving at the clock input of a microprocessor (2) so that parallel synchronism is obtained in stages.

Description

PARALLEL SYNCHRONOUS OPERATION
TECHNICAL HELD
The invention relates to apparatus for providing parallel synchronous operation of at least two micro-processors, in a computer system.
BACKGROUND ART
Modern computers and computer systems often include micro-processors, with which sub-functions are performed. To obtain great reliability in their perfor- mance it is desirable simultaneously to perform the subfunctions in two microprocessors working in parallel. They must operate synchronous to enable comparison of their results. Their clock frequency is controlled by the computer system clock, which has its frequency divided in the clock counters of the microprocessors. There is often a fixed division by a factor of four. If further division is required this is suitably performed with the aid of a JK-flipflop connected to the respective clock input. A problem in synchronizing two or more microprocessors is that their internal functions are inaccessible from outside. It is therefore not possible to achieve parallel synchronism with the aid of a resetting pulse.
DISCLOSURE OF INVENTION
The present invention relates to apparatus, with the aid of which two or more mircroprocessors are brought into parallel synchronous operation. The invention is characterized in the accompanying claims.
BRIEF DESCRIPTION OF DRAWINGS
The invention in accordance with the claims is described hereinafter with the aid of the accompanying drawings, where Figure 1 illustrates one embodiment of the invention and Figure 2 another embodiment. Figure 3 is a time chart for the signals with respect to synchronization. BEST MODE FOR CARRYING OUT THE INVENTION
Figure 1 is a logic diagram where the apparatus comprises a negative exclusive OR circuit 3 and an AND circuit 4 connected to two clock counters 1,2, each associated with a microprocessor 6,7. The computer system clock Cl is connected to the input of the clock counter 1. The output of the circuit 4 is connected to the input of the other clock counter 2, one input of the circuit 4 being connected to the system clock Cl. The frequency of this clock is divided by a factor of four in the clock counters 1,2. The outputs of the latter are each connected to an input of the circuit 3, the output of which is connected to the other input of the circuit 4.
The output of the circuit 3 will be zero for a signal difference at the outputs of the clock counters 1,2. The system clock signal is then prevented by the circuit 4 from reaching the clock counter 2. If there is no difference in the signals on the outputs of the clock counters, the output of the circuit 3 is ONE, and the circuit 4 allows the system clock signals to reach the clock counter 2. From this it follows that for asynchronism between the clock counters, the counter 2 will be periodcally stopped until parallel synchronism occurs (described in detail in connection with Figure 3).
Figure 2 illustrates another embodiment. An arithmetic circuit 5 comprising a JK-flipflop to each microprocessor is connected between the system clock and the microprocessors. The arithmetic circuit divides the system clock frequency by a factor of two, resulting in that the total division of the frequency will be by a factor of eight. The JK inputs to the flipflop having its output connected to the clock input of the other microprocessor 2 are commonly connected to the output of the logical circuit 3. The AND function of the circuit 4 in Figure 1 is thus replaced.
The time chart in Figure 3 illustrates the phasing-in to parallel synchronism between the mircoprocessors, in the case where the frequency of the signal clock Cl is divided by a factor of eight, according to Figure 2. In the chart, A, , B, and C-. depict the frequecy division sequence in the microprocessor 1, while A« B« and C„ depict the frequency division sequence in the microprocessor 2. One of the two most unfavourable cases possible is illustrated in the diagram. For describing the phasing-in a positive period is denoted by a logical ONE and a negative by a logical ZERO. A shifts when Cl goes from O to 1, B shifts when A goes from 1 to O, and C shifts when B goes from 1 to O. The Cl pulses to A2 are stopped at difference between C, and m. According to the chart, this occurs for the first time when C, goes from O to 1 after the Cl period 3. A2 is in the state 1 until the Cl period when C, has gone from 1 to 0, i.e. after the period 8. Then A„ gets the Cl pulse and goes from 1 to 0. At the same time B« goes from 1 to 0 and C2 from 0 to 1. Then there is once again a difference between C, and C2, thus A2 being blocked again for the Cl pulses. This difference prevails until C-, once again goes from 0 to 1, which takes place after the period 11. There is subsequent equality between A, and A2, B-. and B2, C, and C2, i.e. a state of parallel synchronism. Independent what division factor is used for the Cl frequency the phasing-in always takes place at the latest within 1,5 times the cycle time of the clock counters. Figure 3 also explains the phasing-in of the apparatus according to Figure 1, with the difference that the division uses a factor of 4, and thus only the frequency division sequences A and B exist.

Claims

1. Apparatus for providing parallel synchronous operation of a first and a second microprocessor (1,2) in a computer system, where the clock frequency of the microprocessors is obtained by internal division of a system clock frequen¬ cy, characterized in that the apparatus includes a switch (4) for breaking and making the system clock signal path to the clock input of the second microprocessor (2), and a logical circuit (3) for controlling the switch (4), the two inputs of the circuit (3) being connected to the clock outputs of the microprocessors (1,2) such that for signal difference between their inputs the logical circuit causes the switch (4) to break the system clock signal path, while for signal equality on the clock outputs it causes the switch to make said path, a stepwise phasing-in to parallel synchronism thus being attained.
2. Apparatus as claimed in claim 1, characterized in that the logical circuit (3) comprises a negative exclusive OR circuit and in that the switch (4) comprises an AND circuit.
3. Apparatus as claimed in claim 1, characterized in that the switch (4) is included in a dividing arithmetic circuit (5), comprising a first and a second JK- flipflop connected between the system clock and the clock input of a micropro¬ cessor assigned to each flipflop, the second JK flipflop having its output connected to the second microprocessor (2) and its J and K inputs connected to the output of the logical circuit (3), this JK flipflop performing the function of the switch (4).
EP85901643A 1984-03-26 1985-03-26 Parallel synchronous operation Expired EP0175748B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT85901643T ATE42845T1 (en) 1984-03-26 1985-03-26 PARALLEL SYNCHRONOUS OPERATION.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8401661 1984-03-26
SE8401661A SE441709B (en) 1984-03-26 1984-03-26 DEVICE FOR ASTADCOMMA PARALLEL SYNCHRON OPERATION OF A FIRST AND ANOTHER MY PROCESSOR

Publications (2)

Publication Number Publication Date
EP0175748A1 true EP0175748A1 (en) 1986-04-02
EP0175748B1 EP0175748B1 (en) 1989-05-03

Family

ID=20355290

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85901643A Expired EP0175748B1 (en) 1984-03-26 1985-03-26 Parallel synchronous operation

Country Status (22)

Country Link
EP (1) EP0175748B1 (en)
JP (1) JPS61501661A (en)
KR (1) KR900000087B1 (en)
AT (1) ATE42845T1 (en)
AU (1) AU567461B2 (en)
BR (1) BR8506056A (en)
CA (1) CA1229176A (en)
DE (1) DE3569995D1 (en)
DK (1) DK163751C (en)
ES (1) ES8608196A1 (en)
FI (1) FI87703C (en)
GR (1) GR850731B (en)
HU (1) HU192224B (en)
IE (1) IE56467B1 (en)
IN (1) IN163811B (en)
IT (1) IT1184203B (en)
MX (1) MX157111A (en)
NO (1) NO168446C (en)
NZ (1) NZ211383A (en)
PT (1) PT80160B (en)
SE (1) SE441709B (en)
WO (1) WO1985004498A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5020024A (en) * 1987-01-16 1991-05-28 Stratus Computer, Inc. Method and apparatus for detecting selected absence of digital logic synchronism
SE461484B (en) * 1988-06-23 1990-02-19 Ellemtel Utvecklings Ab SETTING AND DEVICE MAKING A START SIGNAL FOR PARALLEL SYNCHRONOUS OPERATION OF THREE MAINLY IDENTICAL DATA PROCESSING UNITS
EP3015971B1 (en) 2014-10-28 2019-07-31 Napatech A/S A system and a method of deriving information

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE406655B (en) * 1976-10-08 1979-02-19 Ellemtel Utvecklings Ab DEVICE FOR TRANSMISSION OF CERTAIN CLOCK SIGNALS IN A CLOCK SIGNAL SERIES BY USE OF LOWER FREQUENCY SIGNALS IN PARTICULAR THAT FROM THAT SIGNALS OF LOWER FREQUENCY RECEIVE WELL-DEFINED PULSE PULSE ...
SU809135A1 (en) * 1979-03-27 1981-02-28 Ордена Октябрьской Революции Всесоюз-Ный Государственный Проектно-Изыска-Тельский И Научно-Исследовательскийинститут "Энергосетьпроект" Device for complex synchronization
AU533076B2 (en) * 1979-10-08 1983-10-27 Control Data Corporation Establishing and maintaining synchronization of data preamble and clock signals

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8504498A1 *

Also Published As

Publication number Publication date
IT8520071A0 (en) 1985-03-26
MX157111A (en) 1988-10-27
BR8506056A (en) 1986-03-25
IE56467B1 (en) 1991-08-14
DE3569995D1 (en) 1989-06-08
NO854306L (en) 1985-10-28
FI87703B (en) 1992-10-30
HUT38456A (en) 1986-05-28
FI854182L (en) 1985-10-25
ATE42845T1 (en) 1989-05-15
FI87703C (en) 1993-02-10
ES541549A0 (en) 1986-06-01
AU567461B2 (en) 1987-11-19
SE441709B (en) 1985-10-28
DK543685D0 (en) 1985-11-25
HU192224B (en) 1987-05-28
AU4118885A (en) 1985-11-01
CA1229176A (en) 1987-11-10
IN163811B (en) 1988-11-12
NZ211383A (en) 1988-10-28
NO168446C (en) 1992-02-19
SE8401661D0 (en) 1984-03-26
ES8608196A1 (en) 1986-06-01
EP0175748B1 (en) 1989-05-03
SE8401661L (en) 1985-09-27
DK543685A (en) 1985-11-25
GR850731B (en) 1985-04-22
IT1184203B (en) 1987-10-22
PT80160A (en) 1985-04-01
DK163751B (en) 1992-03-30
JPS61501661A (en) 1986-08-07
PT80160B (en) 1987-05-29
FI854182A0 (en) 1985-10-25
KR900000087B1 (en) 1990-01-19
NO168446B (en) 1991-11-11
WO1985004498A1 (en) 1985-10-10
DK163751C (en) 1992-09-07

Similar Documents

Publication Publication Date Title
JPH04257932A (en) Chip for emulation for digital signal processor
EP0175748A1 (en) Parallel synchronous operation.
CA1131717A (en) Digital operate/release timer
JPH06244739A (en) Multiplexer circuit
JP2517943B2 (en) Timer device
SU1420653A1 (en) Pulse synchronizing device
JPS61160105A (en) Timing control system
SU1128376A1 (en) Device for synchronizing pulses
SU663104A2 (en) Switching device
SU458829A1 (en) Computer system synchronization device
SU1115239A2 (en) Pulse repetition frequency divider with variable countdown
SU1377860A1 (en) Device for monitoring accumulator
SU1347182A1 (en) Self-monitoring computing device
JP2903548B2 (en) Logic circuit diagnostic system
JPS5911424A (en) Processing circuit of interruption signal
SU572925A1 (en) Switching unit
SU1691954A1 (en) Reserved frequency divider
SU1293732A1 (en) Device for debugging programs
SU960820A2 (en) Multi-channel device for priority-based pulse selection
SU1598169A1 (en) Divider counter
JPS6329301Y2 (en)
SU1319264A1 (en) Pulse shaper
SU1277385A1 (en) Toggle flip-flop
JPS63316236A (en) Interruption control circuit
JPH0661078B2 (en) Computer synchronization method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19851022

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE GB LI NL

17Q First examination report despatched

Effective date: 19880819

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE GB LI NL

REF Corresponds to:

Ref document number: 42845

Country of ref document: AT

Date of ref document: 19890515

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3569995

Country of ref document: DE

Date of ref document: 19890608

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 19980304

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19980406

Year of fee payment: 14

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990331

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990331

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990331

BERE Be: lapsed

Owner name: TELEFONAKTIEBOLAGET L M ERICSSON

Effective date: 19990331

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010306

Year of fee payment: 17

Ref country code: AT

Payment date: 20010306

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20010307

Year of fee payment: 17

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020326

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020326

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20021001

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020326

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20021001

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20040430

Year of fee payment: 20