EP0164292B1 - Mit anodenseitig angeordnetem Gate abschaltbarer Thyristor - Google Patents

Mit anodenseitig angeordnetem Gate abschaltbarer Thyristor Download PDF

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Publication number
EP0164292B1
EP0164292B1 EP19850401035 EP85401035A EP0164292B1 EP 0164292 B1 EP0164292 B1 EP 0164292B1 EP 19850401035 EP19850401035 EP 19850401035 EP 85401035 A EP85401035 A EP 85401035A EP 0164292 B1 EP0164292 B1 EP 0164292B1
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EP
European Patent Office
Prior art keywords
region
anode
metallization
cathode
gate
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Expired
Application number
EP19850401035
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English (en)
French (fr)
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EP0164292A1 (de
Inventor
Robert Pezzani
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Thomson Semiconducteurs SA
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Thomson Semiconducteurs SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices

Definitions

  • the known thyristors are generally formed by the superposition of four semiconductor layers of alternating N and P conductivity types: P type anode region, N type central region, P type trigger region, N type cathode region.
  • the central N-type region is the thickest and the least doped; it is this which serves to ensure the voltage withstand of the thyristor in the blocked state; it is formed from the outset by the starting semiconductor substrate used to manufacture the thyristor.
  • the anode region, of type P is diffused on the rear face of the substrate, then metallized to form an anode electrode.
  • the P-type trigger region is diffused or epitaxied on the front face of the substrate, after which an N-type cathode region is again diffused on the front face, inside the trigger region.
  • This N-type diffusion is localized, that is to say that it does not occupy the entire surface of the patch, in order to leave a surface area for access to the trigger region.
  • a cathode metallization covers the cathode region and a trigger metallization covers the trigger access area.
  • a thyristor normally operates in the following manner: it blocks the current between anode and cathode until a sufficient trigger current is applied. When a trigger current threshold is exceeded, the thyristor trips and becomes conductive. It then remains conductive even if the trigger current disappears, and this until the main current between anode and cathode drops below a specific holding current of the thyristor. The thyristor then blocks again.
  • thyristors are adapted to allow blocking by the trigger (GTO: gate turn off thyristor, that is to say thyristor blockable by the trigger).
  • GTO gate turn off thyristor, that is to say thyristor blockable by the trigger.
  • a negative current is applied to the trigger to block these thyristors even when they are traversed by a main current, between anode and cathode, much higher than their holding current.
  • These thyristors notably have interdigitated cathode and trigger structures so that the trigger can act as much as possible under the cathode region.
  • the present invention proposes to completely modify the usual structure of the thyristors, and to produce a thyristor with a heavily doped N + type trigger region situated between the lightly doped N layer forming the starting substrate and an anode region, access to the trigger region being via the surface of the chip of the side of the anode.
  • the thyristor according to the invention consists of a semiconductor wafer formed from a starting substrate of type N with little doping, the wafer mainly comprising regions of alternating conductivity types and surface metallizations of anode, cathode, and trigger; the anode and trigger metallizations are located on a first face of the patch and the cathode metallization on the second face; the alternating semiconductor regions are as follows: lightly doped region N of the starting substrate constituting a first central layer; heavily doped N + region constituting a trigger region on one side of the first central region; region P diffused locally in the trigger region over only part of the depth thereof and constituting an anode region, the trigger region and the anode region both being flush on the first face of the patch and being covered respectively by the trigger metallization and the anode metallization; lightly doped region P constituting a second central region on the other side of the first central region; region N diffused locally in the second central region of type P and constituting a region c
  • N-type starting substrate which is easier and therefore less costly indutrially
  • the passage of current from the trigger under the anode is made easier and the carriers accumulated in the central region N during the conduction of the thyristor can be more easily evacuated by a negative trigger current intended to block the thyristor.
  • thyristors blockable by the trigger having a trigger situated on the side of the anode have never been produced because it has always been considered not only that there was no interest in doing so but that there had as a significant drawback the need to diffuse a P-type region (anode) inside a fairly heavily doped N-type region, which is much more difficult than to diffuse a P-type region in an N substrate lightly doped or a heavily doped N-type region in a moderately doped P-type region (usual case of thyristors).
  • the present invention therefore proposes to reconsider this prejudice to allow an improvement of the thyristors lockable by the trigger.
  • the sparsely doped central region is designated by N1, the trigger region by P1, the cathode region by N2, the anode region by P2, the anode metallization by 10 (lower face), the cathode metallization by 12 and the trigger metallization by 14, both on the upper face.
  • the cathode and trigger regions are interdigitated on the upper surface of the patch, as well as the corresponding metallizations, that is to say that portions of the trigger region P1 are flush with the surface between portions of the region of N2 cathode.
  • the outcrops of the trigger region are recessed relative to the outcrops of the cathode region to facilitate separation between the contact on the cathode metallization and the contact on the trigger metallization.
  • a passivation insulator 16 is provided on the non-metallized parts of the upper surface.
  • the thyristor structure which can be opened by the trigger according to the invention is shown in FIG. 2.
  • N1 a lightly doped N-type central layer forming most of the starting substrate from which the thyristor is formed. This layer N 1 will be called the first central region.
  • a heavily doped cathode region N2 is diffused; this diffusion is preferably localized and lets appear areas (and in particular short-circuit holes) where the region P1 is exposed on the rear face (second face) of the semiconductor patch constituting the thyristor.
  • the entire rear surface is covered with a cathode metallization 12 which comes into contact with both the region N2 (cathode) and portions of the region P1 (second central region).
  • anode region P2 On the other side of the first central region N1, there is a heavily doped layer N3, which is the trigger region in which is locally diffused, over only part of its thickness, an anode region P2.
  • Trigger region access areas N3 are provided between anode region portions P2, preferably interdigitated in the form of fine anode and trigger fingers. In these access zones to the gate region N3, this region rises to the surface (first face) of the patch, and it can be expected that the access zones are even more doped than the gate region N3; this is why these areas have been designated by the reference N4.
  • the anode regions P2 are covered with an anode metallization 10, while the areas N4 of access to the trigger region N3 are covered with a trigger metallization 14. These metallizations are prohibited like the regions that they overlap. Between the metallization portions, the non-metallized surface is covered by a passivation insulator 16.
  • the anode regions P2 and corresponding metallizations 10 are in relief with respect to the access zones to the trigger N4 and to the corresponding metallizations 14 to facilitate the separation of the contacts made with these metallizations.
  • cathode regions N2 in front of the anode regions P2 there are cathode regions N2, possibly with one or more small central short-circuit desensitization holes where the region P1 joins the cathode metallization, while opposite the regions N4, other, larger zones of the region P1 join the cathode metallization.
  • the edges of the patch are strongly bevelled to reduce the risk of breakdown at the junction exposures N1-P1 and the bevel is formed in a direction such that the beveled edge makes an acute angle with the face corresponding to the cathode. , and an obtuse angle with the face corresponding to the anode, that is to say the opposite of what is provided for the usual thyristors. This angle is here in the direction favorable to improving the voltage withstand of the thyristor.
  • the bevelled edge of the wafer is covered with a passivation insulator 18.
  • N-type silicon washer whose doping is chosen according to the usual rules as a function of the desired voltage withstand.
  • the order of magnitude is some 10 13 atoms / cm 3 of type N impurities.
  • a more heavily doped N-type surface layer is produced by diffusion, implantation or epitaxy, which will constitute the layer N3.
  • Doping impurity is arsenic, phosphorus or antimony. If this layer is not produced by epitaxy, heat treatment is carried out at a temperature of 1,000 to 1,300 ° C to finally obtain an N3 coating of 20 to 80 f lm, deep with a surface concentration. from 10 1 6 to 10 19 atoms / cm3.
  • P-type diffusion is carried out (aluminum or gallium for example) to form the layers P1 and P2 on the second and first faces respectively.
  • This layer is etched on the side of the region P2 to strip the areas of access to the trigger region, and the silicon is excavated in the stripped places, chemically or by plasma to obtain a sufficient drop in the trigger (5 to 40 microns ).
  • N-type dopant (arsenic or phosphorus) is then diffused, so as to simultaneously produce the layers N2 and N4 over a depth of 5 to 40 gm, with a surface concentration greater than that of the layer P1.
  • the silicon wafer is then oxidized or covered with a deposited oxide; windows are open in the oxide facing the layers N4 and P2 so as to allow the surface metallization of these layers; the outcrops of the junctions between the layers N4 and P2 remain covered with oxide.
  • the oxide is completely removed on the second face; the silicon washer is cut if necessary into individual pellets each corresponding to a thyristor (laser cutting for example).
  • the surfaces not covered with oxide are metallized (nickel metallization carried out for example by dipping).
  • the lateral surface of the pellet is mechanically machined in a beveled shape (truncated cone or pyramid, the largest surface of which is that of the cathode).
  • the acute angle is about 40 to 60 °.
  • the machined surface is chemically attacked and then covered with a mineral or organic passivation insulator.
  • the pellet is then mounted in a housing from which three electrodes emerge.
  • this thyristor it is also the central layer N1 which contains the maximum of charges accumulated during a conduction period; at the time of blocking, these charges can be evacuated not only by the short-circuit holes and by natural recombination, but also by the trigger. This leads to a good compromise between the ease of priming and the ease of blocking the thyristor, avoiding in both directions the consumption of a too large trigger current.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Claims (5)

1. Über die Zundelektrode (14) blockierbarer Thyristor, bestehend aus einem Halbleiterplättchen, das ausgehend von einem gering dotierten Substrat vom N-Typ gebildet wird, wobei das Plättchen hauptsächlich Bereiche abwechselnder Leitfähigkeitstypen und oberflächliche Metallisierungen für die Anode (10), die Kathode (12) und die Zündelektrode (14) besitzt, dadurch gekennzeichnet, daß die Anoden- und Zündelektrodenmetallisierungen (10, 14) auf einer ersten Seite des Plättchens und die Kathodenmetallisierung (12) auf einer zweiten Seite des Plättchens angebracht sind, und daß die abwechselnden Bereiche folgende sind: gering dotierter N-Bereich des Ausgangssubstrats, der eine erste zentrale Schicht (N1) bildet, stark dotierter NAlt-Bereich, der einen Zündelektrodenbereich (N3) auf einer Seite des ersten zentralen Bereichs bildet, P-Bereich, der örtlich in den Zündelektrodenbereich über nur einen Teil der Tiefe dieses Bereichs diffundiert ist und einen Anodenbereich (P2) bildet, wobei der Zündelektrodenbereich und der Anodenbbereich beide auf der ersten Seite des Plättchens zutagetreten und von einer Zündelektrodenmetallisierung (14) bzw. Anodenmetallisierung (10) bedeckt sind, gering dotierter P-Bereich, der einen zweiten zentralen Bereich (P1) auf der anderen Seite des ersten zentralen Bereichs bildet, N-Bereich, der örtlich in den zweiten zentralen Bereich vom P-Typ diffundiert ist und einen Kathodenbereich (N2) bildet, der von der Kathodenmetallisierung (12) bedeckt ist, welche gleichmäßig auf den größten Teil der zweiten Seite des Plättchens aufgebracht ist.
2. Thyristor nach Anspruch 1, dadurch gekennzeichnet, daß die Zündelektrodenmetallisierung (14) und die Anodenmetallisierung (10) ineinander verzahnt sind.
3. Thyristor nach Anspruch 1, dadurch gekennzeichnet, daß die Zonen, in denen der Zündelektrodenbereich (N3) auf der ersten Seite des Plättchens zutagetritt, bezüglich der Zonen zurückgesetzt sind, in denen der Anodenbereich (P2) auf derselben Seite zutagetritt.
4. Thyristor nach Anspruch 1, dadurch gekennzeichnet, daß die Ränder des Plättchens abgeschrägt sind und einen spitzen Winkel mit der Seite der Kathode sowie eine stumpfen Winkel mit der Seite der Anode bilden.
5. Thyristor nach Anspruch 1, dadurch gekennzeichnet, daß Kurzschlußlöcher vorgesehen sind, durch die der zweite zentrale Bereich (P1) durch den Kathodenbereich (N2) hindurch bis zur Kathodenmetallisierung (12) vordringt.
EP19850401035 1984-05-30 1985-05-28 Mit anodenseitig angeordnetem Gate abschaltbarer Thyristor Expired EP0164292B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8408493 1984-05-30
FR8408493A FR2565409B1 (fr) 1984-05-30 1984-05-30 Thyristor blocable a gachette d'anode

Publications (2)

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EP0164292A1 EP0164292A1 (de) 1985-12-11
EP0164292B1 true EP0164292B1 (de) 1987-10-14

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DE (1) DE3560781D1 (de)
FR (1) FR2565409B1 (de)

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Publication number Priority date Publication date Assignee Title
JPS624368A (ja) * 1985-06-28 1987-01-10 シ−メンス、アクチエンゲゼルシヤフト サイリスタ
CH670528A5 (de) * 1986-03-20 1989-06-15 Bbc Brown Boveri & Cie
DE3832208A1 (de) * 1988-09-22 1990-03-29 Asea Brown Boveri Steuerbares leistungshalbleiterbauelement
CN108550572B (zh) * 2018-03-02 2023-08-25 中国工程物理研究院电子工程研究所 碳化硅门极可关断晶闸管gto的器件阵列与其制备方法

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US4089024A (en) * 1972-09-20 1978-05-09 Hitachi, Ltd. Semiconductor switching device
GB1558840A (en) * 1977-02-07 1980-01-09 Rca Corp Gate controlled semiconductor device
JPS5933272B2 (ja) * 1978-06-19 1984-08-14 株式会社日立製作所 半導体装置

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FR2565409B1 (fr) 1986-08-22
EP0164292A1 (de) 1985-12-11
DE3560781D1 (en) 1987-11-19
FR2565409A1 (fr) 1985-12-06

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