EP0155018A1 - Arrangement of supervising the functions of a memory device - Google Patents

Arrangement of supervising the functions of a memory device Download PDF

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Publication number
EP0155018A1
EP0155018A1 EP85200133A EP85200133A EP0155018A1 EP 0155018 A1 EP0155018 A1 EP 0155018A1 EP 85200133 A EP85200133 A EP 85200133A EP 85200133 A EP85200133 A EP 85200133A EP 0155018 A1 EP0155018 A1 EP 0155018A1
Authority
EP
European Patent Office
Prior art keywords
sub
arrangement
parity
memory device
supervising
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85200133A
Other languages
German (de)
English (en)
French (fr)
Inventor
Hans Hendrik Verheul
Martinus Petrus Paulus De Wit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0155018A1 publication Critical patent/EP0155018A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity

Definitions

  • the invention relates to an arrangement for supervising the functions of a memory device for storing parity bit-containing data words, each having m bits (m > 2) the arrangement comprising dividing means for dividing the data words into n (n ⁇ 2) sub-data words, and the memory device comprising n separate sub-memory devices each coupled to the dividing means for storing a sub-data word in each of the n sub-memory devices.
  • the invention has for its object to provide an arrangement for supervising a memory device, with which the write, storage and addressing functions are supervised in a simple way.
  • an arrangement of the type set forth in the opening paragraph is characterized in that the arrangement comprises a parity checking device connected to the sub-memory devices for checking the parity of the n associated sub-data words which form one data word.
  • sub-memory devices consist of (e.g. physically) separate circuits
  • the risk that they will make the same errors at the same time is so small as to be disregarded, so that generally an error in the write, memory or addressing function in one of the circuits will be defected almost without exception.
  • the sub-data words each comprise m/n bits and each memory location of the sub-memory devices can also contain m/n bits.
  • the dividing means comprises a register having m bit positions and for the register to have n (groups of) outputs for the respective m/n-bits sub-data words.
  • Dividing means R in Fig. 1 have an input IN for receiving data words DW.
  • the dividing means can more specifically be consituted by a register having as many bit positions as there are bits in the data words, for example m (m # 2).
  • the dividing means divide a data word DW into a number n of sub-data words SDW.
  • the further detailed description of Fig. 1 is based on the assumption that an m-bit data word is divided into 3 sub-data words each having m/3 bits, namely SDW 1 , SDW 2 and SLW 3 .
  • the data word DW includes a parity bit PB which in the example shown in Fig. 1 occupies the last bit position. With the aid of the parity bit it can be checked whether the parity of the (m-1) data bits is correct, that is to say whether the m-bit data word contains either an even or an odd number of "ones" or "zeroes".
  • the three (generally n) sub-data words are transferred to sub-registers SR 1 , SR 2 and SR 3 via their respective outputs O 1 , 0 2 and 0 3 at an instant determined by write pulses WP 1 , WP 2 and WP 3 .
  • the sub-registers SR i are formed by (e.g. physically) separate, therefore independently realised circuits and are activated by write pulses which are also generated independently of each other.
  • Outputs of sub-registers SR i are connected to a prior art parity checking arrangement PC, which determines whether the generated parity across the m-1 data bits (m/n from SR , m/n from SR 2 and (m/n) -1 from SR 3 ) corresponds to the transferred parity (last bit in SR 3 ).
  • An output OUT of the parity checking arrangement PC supplies a signal which is indicative of whether the parity is correct or not correct.
  • the arrangement shown in Fig. 1 does not comprise sub-registers SR i each having one memory location, but comprises sub-memory devices M i which, as shown in Fig. 2, have n memory locations.
  • the sub-data word SDW i is then entered into the memory location determined by the address decoder MA 1 .
  • the address decoder MA i determines this location on the basis of the applied addressing information AP i .
  • the above description of the embodiment is based on the assumption that the data word is divided into sub-data words each comprising an equal number of bits, namely m/n bits. This is, however, not absolutely necessary: the invention is also suitable for use with embodiments using any other dividing mode. Obviously the number of bits which must be available per memory location in each sub-memory device must be in agreement with the selected dividing mode.
  • each sub-register or each sub-memory device must be activated with a separately generated write pulse.
  • this write pulse is supervised separately. This supervision may be omitted when this pulse is doubled (generally made into a multiple).
  • the generation of the write pulses for a plurality of sub-registers or a plurality of sub-memory devices may be combined without any objection, provided that always at least two independent write pulses are used.
  • three sub-data words are formed each comprising 4 bits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
EP85200133A 1984-02-08 1985-02-07 Arrangement of supervising the functions of a memory device Withdrawn EP0155018A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8400392A NL8400392A (nl) 1984-02-08 1984-02-08 Inrichting voor de functiebewaking van een geheugeninrichting.
NL8400392 1984-02-08

Publications (1)

Publication Number Publication Date
EP0155018A1 true EP0155018A1 (en) 1985-09-18

Family

ID=19843452

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85200133A Withdrawn EP0155018A1 (en) 1984-02-08 1985-02-07 Arrangement of supervising the functions of a memory device

Country Status (4)

Country Link
EP (1) EP0155018A1 (ja)
JP (1) JPS60181855A (ja)
CA (1) CA1223077A (ja)
NL (1) NL8400392A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0520691A1 (en) * 1991-06-28 1992-12-30 Sun Microsystems, Inc. Method and apparatus for non-atomic level parity protection for storing data in random access memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4918824B2 (ja) * 2006-08-18 2012-04-18 富士通株式会社 メモリコントローラおよびメモリ制御方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972033A (en) * 1973-12-27 1976-07-27 Honeywell Information Systems Italia Parity check system in a semiconductor memory
EP0080354A2 (en) * 1981-11-23 1983-06-01 Sperry Corporation Computer memory checking system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972033A (en) * 1973-12-27 1976-07-27 Honeywell Information Systems Italia Parity check system in a semiconductor memory
EP0080354A2 (en) * 1981-11-23 1983-06-01 Sperry Corporation Computer memory checking system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
XEROX DISCLOSURE JOURNAL, vol. 1, no. 3, March 1976, page 79, Stamford, Conn., US; R. VIERSON et al.: "Memory parity checking" *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0520691A1 (en) * 1991-06-28 1992-12-30 Sun Microsystems, Inc. Method and apparatus for non-atomic level parity protection for storing data in random access memory
US5325375A (en) * 1991-06-28 1994-06-28 Sun Microsystems, Inc. Method and apparatus for non-atomic level parity protection for storing data in a random access memory

Also Published As

Publication number Publication date
JPS60181855A (ja) 1985-09-17
CA1223077A (en) 1987-06-16
NL8400392A (nl) 1985-09-02

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): BE DE FR GB IT SE

17P Request for examination filed

Effective date: 19860317

17Q First examination report despatched

Effective date: 19881130

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19890613

RIN1 Information on inventor provided before grant (corrected)

Inventor name: VERHEUL, HANS HENDRIK

Inventor name: DE WIT, MARTINUS PETRUS PAULUS