EP0153650B1 - Dünnschichthybridschaltung - Google Patents

Dünnschichthybridschaltung Download PDF

Info

Publication number
EP0153650B1
EP0153650B1 EP19850101472 EP85101472A EP0153650B1 EP 0153650 B1 EP0153650 B1 EP 0153650B1 EP 19850101472 EP19850101472 EP 19850101472 EP 85101472 A EP85101472 A EP 85101472A EP 0153650 B1 EP0153650 B1 EP 0153650B1
Authority
EP
European Patent Office
Prior art keywords
layer
inorganic protective
contact areas
thin
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19850101472
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0153650A3 (en
EP0153650A2 (de
Inventor
Hans-Joachim Dr. Dipl.-Phys. Krokoszinski
Henning Dr. Dipl.-Phys. Oetzmann
Conrad Dr. Dipl.-Phys. Schmidt
Dieter Dipl.-Ing. Gilbers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASEA BROWN BOVERI AKTIENGESELLSCHAFT
Original Assignee
ASEA BROWN BOVERI AG
Asea Brown Boveri AG Germany
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASEA BROWN BOVERI AG, Asea Brown Boveri AG Germany filed Critical ASEA BROWN BOVERI AG
Publication of EP0153650A2 publication Critical patent/EP0153650A2/de
Publication of EP0153650A3 publication Critical patent/EP0153650A3/de
Application granted granted Critical
Publication of EP0153650B1 publication Critical patent/EP0153650B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/017—Glass ceramic coating, e.g. formed on inorganic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0585—Second resist used as mask for selective stripping of first resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Definitions

  • the invention relates to a method for producing a thin-film hybrid circuit with contact areas for external connections and / or components.
  • Such a thin film hybrid circuit is known from H.-J. Hanke, H. Fabian, "Technology of electronic assemblies", 3rd edition 1982, VEB Verlagtechnik, Berlin, page 92 known.
  • conductor tracks, resistors and capacitors are vapor-deposited or sputtered on a substrate using thin-film technology, while for connecting active components, e.g. Transistors, as well as contact surfaces for connecting external lines are provided.
  • active components e.g. Transistors
  • a passivation layer is desirable for such thin-film hybrid circuits for several reasons.
  • the vapor-deposited or sputtered structures are not sufficiently scratch-resistant and are therefore easily damaged during an assembly and «packaging» process (installation in a housing).
  • the copper and aluminum conductor tracks of the thin-film circuit corrode when stored in moist air for a long time.
  • a thick organic layer eg photoresist
  • an inorganic layer e.g. Al 2 0 3 or Si
  • the invention is based on the object of producing a passivation layer for a thin-layer hybrid circuit of the type mentioned at the beginning, which at the same time is sufficiently scratch-resistant, resistant to chemical baths, tight against water vapor diffusion and temperature-resistant up to approximately 350 ° C.
  • the passivation layer sequence inorganic protective layer and hardened photoresist layer ensures protection of the thin-layer hybrid circuit against oxidation, corrosion, water vapor diffusion, mechanical damage and chemical baths.
  • 1 to 6 show the individual method steps for applying the passivation layer sequence for thin-film circuits.
  • the fully evaporated or sputtered thin-film circuit shown in FIG. 1 serves as the output circuit.
  • a base oxide layer 2 and, for example, a conductor track layer 3 are applied to a substrate 1 (e.g. glass).
  • the conductor track layer 3 is connected to a contact area (bonding or soldering pads) consisting of an NiCr layer 4 applied to the oxide layer 2 and an overlying Ni layer 5.
  • the thin-layer circuit is homogeneously vaporized or sputtered with an inorganic protective layer 6, for example Al 2 O 3 , Si 3 N 4 or glass, which leads to the circuit shown in FIG. 2.
  • the inorganic protective layer 6 protects the metallic layers, such as interconnect layer 3 or Ni layer 5, against oxidation during the subsequent annealing process.
  • the circuit is tempered in air at an aging temperature of 300 to 350 ° C and serves to stabilize the resistances of the thin-film circuit, ie to achieve a high long-term constancy and a low temperature drift.
  • the circuit covered and tempered in this way is homogeneously coated with a photoresist layer 7 in a next method step, which leads to the circuit shown in FIG. 3.
  • the contact areas (layers 4, 5) of the circuit are exposed photolithographically by exposure through a mask and subsequent development, as shown in FIG. 4.
  • the next step in the process is the curing of the photoresist layer 7 at a temperature which is higher than the soldering temperature which occurs when the contact surfaces are soldered.
  • the inorganic protective layer 6 (A1 2 O 3 , Si 3 N 4 or glass) is then etched away on the contact surfaces (NiCr layer 4, Ni layer 5), which leads to the circuit shown in FIG. 5.
  • the contact surfaces are then available with a non-oxidized surface for chemical nickel plating and / or gold plating.
  • the Ni layer 5, as shown in FIG. 6, can be provided with a further Ni layer 8 and an overlying Au layer 9. This «chemical amplification» can also take place in non-neutral baths.
  • the passivation layer sequence produced in this way (inorganic protective layer 6 and hardened photoresist layer 7) has the following advantages:
  • the inorganic protective layer 6 is temperature-resistant and tight against water vapor. It protects the circuit against oxi dation during tempering and against corrosion by air humidity (long-term stability).
  • the hardened photoresist layer 7 is sufficiently smudge-proof and scratch-resistant, ie more resistant to mechanical damage. It can be structured photolithographically and is resistant to non-neutral baths. As a result, it enables selective etching of the inorganic protective layer 6 at the contact areas and protects the remaining circuitry during the chemical amplification of the contact areas. In addition, it acts as a solder stop layer in the assembly process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Formation Of Insulating Films (AREA)
EP19850101472 1984-03-02 1985-02-12 Dünnschichthybridschaltung Expired EP0153650B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3407784 1984-03-02
DE19843407784 DE3407784A1 (de) 1984-03-02 1984-03-02 Duennschichthybridschaltung

Publications (3)

Publication Number Publication Date
EP0153650A2 EP0153650A2 (de) 1985-09-04
EP0153650A3 EP0153650A3 (en) 1986-11-05
EP0153650B1 true EP0153650B1 (de) 1989-11-08

Family

ID=6229455

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19850101472 Expired EP0153650B1 (de) 1984-03-02 1985-02-12 Dünnschichthybridschaltung

Country Status (3)

Country Link
EP (1) EP0153650B1 (enrdf_load_stackoverflow)
JP (1) JPS60206192A (enrdf_load_stackoverflow)
DE (1) DE3407784A1 (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3735959A1 (de) * 1987-10-23 1989-05-03 Bbc Brown Boveri & Cie Mehrlagige duennschichtschaltung sowie verfahren zu deren herstellung
JPH0340486A (ja) * 1989-07-07 1991-02-21 Asahi Chem Ind Co Ltd 印刷配線基板
RU2133523C1 (ru) * 1997-11-03 1999-07-20 Закрытое акционерное общество "Техно-ТМ" Трехмерный электронный модуль
DE10241589B4 (de) 2002-09-05 2007-11-22 Qimonda Ag Verfahren zur Lötstopp-Strukturierung von Erhebungen auf Wafern
DE10320561B4 (de) * 2003-05-07 2007-12-06 Qimonda Ag Verfahren zur Herstellung einer leitfähigen Verbindung zwischen einem Halbleiterchip und einer äußeren Leiterstruktur
JP4652179B2 (ja) 2005-09-05 2011-03-16 日東電工株式会社 配線回路基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001870A (en) * 1972-08-18 1977-01-04 Hitachi, Ltd. Isolating protective film for semiconductor devices and method for making the same
JPS49100970A (enrdf_load_stackoverflow) * 1973-01-22 1974-09-24
DE2548060C2 (de) * 1975-10-27 1984-06-20 Siemens AG, 1000 Berlin und 8000 München Halbleitervorrichtung und Verfahren zu ihrer Herstellung
JPS52132397A (en) * 1976-04-30 1977-11-07 Nippon Chemical Ind Thinnfilm resistor whose resistive temperature coefficient has been improved
US4275407A (en) * 1977-09-01 1981-06-23 Honeywell Inc. Durable insulating protective layer for hybrid CCD/mosaic IR detector array
DE2823881C3 (de) * 1978-05-31 1982-03-18 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von elektrischen Dünnschichtschaltungen für die Herstellung integrierter Leiterbahnüberkreuzungen
GB2046024B (en) * 1979-03-30 1983-01-26 Ferranti Ltd Circuit assembly

Also Published As

Publication number Publication date
JPS60206192A (ja) 1985-10-17
EP0153650A3 (en) 1986-11-05
EP0153650A2 (de) 1985-09-04
DE3407784C2 (enrdf_load_stackoverflow) 1988-11-10
DE3407784A1 (de) 1985-09-12

Similar Documents

Publication Publication Date Title
US3801880A (en) Multilayer interconnected structure for semiconductor integrated circuit and process for manufacturing the same
US4118595A (en) Crossovers and method of fabrication
DE2638799B2 (de) Verfahren zur Verbesserung der Haftung von metallischen Leiterzügen auf Polyimidschichten in integrierten Schaltungen
DE1764951B1 (de) Mehrschichtige metallisierung fuer halbleiteranschluesse
EP0973020A1 (de) Elektrischer Temperatur-Sensor mit Mehrfachschicht
EP0147640A1 (de) Verfahren zur galvanischen Herstellung metallischer, höckerartiger Anschlusskontakte
DE2326314A1 (de) Verfahren zur herstellung einer passivierenden schicht mit wenigstens einer kontaktoeffnung
EP0016251B1 (de) Elektronische Dünnschichtschaltung und deren Herstellungsverfahren
DE2709933A1 (de) Verfahren zum herstellen durchgehender metallischer verbindungen zwischen mehreren metallisierungsebenen in halbleitervorrichtungen
DE2428373A1 (de) Verfahren zum herstellen einer halbleitervorrichtung
EP0153650B1 (de) Dünnschichthybridschaltung
EP1766648B1 (de) Schmelzsicherung für einen chip
DE3639604A1 (de) Verfahren zur herstellung lotverstaerkter leiterbahnen
WO2001084562A1 (de) Temperaturmessfühler und verfahren zur herstellung desselben
DE3127356A1 (de) Verfahren zum bilden elektrisch leitender durchdringungen in duennfilmen
DE2926516A1 (de) Verfahren zur herstellung eines metallfolienwiderstandes und metallfolienwiderstand
DE2136201C3 (de) Verfahren zum Anbringen metallischer Zuleitungen an einem elektrischen Festkörper-Bauelement
DE2550512A1 (de) Verfahren zur herstellung einer metallisierung auf einem substrat
DE4115316A1 (de) Duennfilm-mehrlagenschaltung und verfahren zur herstellung von duennfilm-mehrlagenschaltungen
DE1764937C3 (de) Verfahren zur Herstellung von Isolationsschichten zwischen mehrschichtig übereinander angeordneten metallischen Leitungsverbindungen für eine Halbleiteranordnung
DE1965565A1 (de) Halbleitervorrichtung
WO2004100259A2 (de) Halbleiterbauelement und verfahren zum herstellen eines halbleiterbauelements
DE3704547A1 (de) Verfahren zur herstellung von loetpads und bondpads auf duennschichthybridschaltungen
DE1764977C2 (de) Verfahren zum Herstellen einer Kunststoff-Schutzschicht auf der Oberfläche eines Halbleiterbauelements
DE3721929C2 (enrdf_load_stackoverflow)

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): BE CH FR GB IT LI NL SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): BE CH FR GB IT LI NL SE

17P Request for examination filed

Effective date: 19870422

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ASEA BROWN BOVERI AKTIENGESELLSCHAFT

17Q First examination report despatched

Effective date: 19890411

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): BE CH FR GB IT LI NL SE

ITF It: translation for a ep patent filed
ET Fr: translation filed
GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19901112

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19901113

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19901115

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 19901203

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19901219

Year of fee payment: 7

ITTA It: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19910228

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19920212

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19920213

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Effective date: 19920228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19920229

Ref country code: CH

Effective date: 19920229

BERE Be: lapsed

Owner name: ASEA BROWN BOVERI A.G.

Effective date: 19920228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19920901

GBPC Gb: european patent ceased through non-payment of renewal fee
NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19921030

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

EUG Se: european patent has lapsed

Ref document number: 85101472.0

Effective date: 19920904