EP0140456A1 - Système de traitement de données dans lequel des mots non fiables de la mémoire sont remplacés par un indicateur de non-fiabilité - Google Patents

Système de traitement de données dans lequel des mots non fiables de la mémoire sont remplacés par un indicateur de non-fiabilité Download PDF

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Publication number
EP0140456A1
EP0140456A1 EP84201565A EP84201565A EP0140456A1 EP 0140456 A1 EP0140456 A1 EP 0140456A1 EP 84201565 A EP84201565 A EP 84201565A EP 84201565 A EP84201565 A EP 84201565A EP 0140456 A1 EP0140456 A1 EP 0140456A1
Authority
EP
European Patent Office
Prior art keywords
data
word
memory
unreliability
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84201565A
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German (de)
English (en)
Other versions
EP0140456B1 (fr
Inventor
Theodorus Gerardus Johannes Antonius Martens
Frits Anthonie Steenhof
Johannes Jozef Wilhelmus Kalfs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Gloeilampenfabrieken NV
Publication of EP0140456A1 publication Critical patent/EP0140456A1/fr
Application granted granted Critical
Publication of EP0140456B1 publication Critical patent/EP0140456B1/fr
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information

Definitions

  • the invention relates to a data processing system, comprising a first data input for receiving data which is organized in data blocks, each data block containing at least one data word and check bits, said first data input being connected to an input of a verifier which serves to verify, under the control of the check bits, whether the data block contains reliable data, and to generate an unreliability signal when a data word does not contain reliable data, said first data input also being connected to a memory for the storage of data words.
  • a data processing system of this kind is known from GB 2,084,363. For each data block received, the verifier verifies, under the control of a check bit associated with that data block, whether the data block contains reliable or unreliable data. When the datablock contains unreliable data, the verifier generates an unreliability signal. Under the control of this unreliability signal, the writing of that unreliable data block into the memory is prevented. Thus, only reliable data words are stored in a memory.
  • the data processing system in accordance with said British Patent Application also comprises a separate error flag memory in which, each time when an unreliability signal is generated, an error flag is stored for the unreliable data word in question.
  • error flag memory is required for the storage of error flags each of which indicates that an unreliable data word has occurred in a data blocli said unreliable data word not being stored in the memory.
  • An error flag of this kind often consists of one bit and the data word consists of 8 bits.
  • the memory is, for example a 2K x 8 bit RAM
  • the error flag memory would then comprise a 2K x 1 bit RAM. This requires additional chip surface area or printed circuit board area.
  • a 2K x 8 bit RAM is a common commercial type but this implies that the 2K x 1 bit RAM forms a separate memory which must be separated controlled, so that it requires additional energy and control means.
  • the use of, for example, a specially designed 2K x 9 bit RAM is undesirable for commercial applications because of the design and manufacturing costs.
  • a data processing system in accordance with the invention is characterized in that it also comprises a selection unit and a generator for generating an unreliability indicator, a first input of said selection unit being connected to the first data input, a second input being connected to an output of the generator, and a third input being connected to the verifier in order to receive the unreliability signal, an output of said selection unit being connected to a second data input associated with the memory, said selection unit being provided in order to block said first input under the control of an unreliability signal received and to substitute an unrealibility indicator presented to the second input for the data word containing unreliable data.
  • the unreliable data word is not written into the memory but is replaced by an unreliability indicator presented to the second input of the selection unit. Because the unreliability indicator is now written in the memory in the location of the unreliable word, it is no longer necessary to use a separate memory. When the memory is read, it is unambiguously indicated whether or not the data word read is reliable.
  • a first preferred embodiment of the data processing system i" accordance with the invention is characterized in that the unreliability indicator has the same word length as the data word. Consequently, all bit locations at the relevant memory address are directly provided with bits without separate generators being required for this purpose.
  • a second preferred embodiment of the data processing system in accordance with the invention is characterized in that the unreliability indicator comprises an exception word.
  • an exception word as an unreliability indicator, the risk,that a reliable data word which could otherwise correspond to the unreliability indicator so that it would incorrectly be deemed unreliable is substantially reduced to zero.
  • a further preferred embodiment of a data processing system in accordance with the invention is characterized in that a data word contains 8 bits, the unreliability indicator being formed by the data word 1000 0000.
  • the data word 1000 0000 corresponds to the full scale input range of the AD converter. This full scale input range hardly ever occurs, because severe distortion due to clipping occurs when this range is overstepped.
  • Another preferred embodiment of a data processing system in accordance with the invention is characterized in that the memory is of the small outline package type.
  • Small outline package type memories are memories which occupy only very little chip surface area.
  • a separate flag bit memory is saved by utilizing a data processing system in accordance with the invention, even more chip surface area is saved.
  • this flat bit memory is omitted, no sepate memory connections are required either for this memory, so that surface area is saved again.
  • no separate addressing is required for the flag bit memory, which benefits the processing time.
  • the invention also relates to a method of writing data words into a memory which forms part of a data processing system, said method comprising the following steps:
  • a method in accordance with the invention is characterized in that, when it has been verified that the data word contains unreliable data, the unreliable data word in question is replaced by an unreliability indicator which is written at the address specified for the data word in question.
  • the writing of reliable data words into the memory is preceded by the writing of unreliability indicators, each reliable data word then erasing the unreliability indicator written at its specified address.
  • each reliable data word then erasing the unreliability indicator written at its specified address.
  • the inve ion can be used in any data processing system utilizing an indicator to indicate that a data word contains unreliable data.
  • the invention will be described in detail hereinafter with reference to an embodiment in which the data processing system forms part of a PCM audio system according to the 8 mm video format.
  • PCM pulse code modulation
  • the data is transported in data blocks.
  • Fig. 1 shows an example of such a data block.
  • the first three bit positions contain the synchronization signal (S) for synchronizing the various data blocks in the data stream and the data words of a data block.
  • the next 8 bits contain an address word (Add) for a location in a memory.
  • the data words forming part of the data block in question are written into the memory, for example a RAM.
  • the addressing of the memory is determined by means of the address word from the data block.
  • the 80 subsequent bits comprise 10 8-bit words (w l -w n ) which contain digitized audio data and/or error correction data.
  • the next 16 bits (cw) contain check bits whose contents provide an indication concerning the correct reception of the data block. These check bits are generated, for example by means of a cyclic redundancy check (CRC) or other error detection code.
  • CRC cyclic redundancy check
  • Fig. 2 shows an embodiment of a memory at the receiving side of a digital audio system.
  • Each of the numbers 1 to 1570 in the figure represents an octad or a group of 8 bits (one byte), thus representing a location in the memory for the storage of one data word.
  • the memory thus has a capacity of 157 x 10 words.
  • the words received are stored in the memory, the starting address being equal to the address forming part of the data block whereto the data words belonged.
  • the memory also comprises space (C) forthe storage of the check bits.
  • the words forming part of the data block in question are checked as regards reliability. This is performed by means of the check bits which form part of the data block. For example, by utilizing the known cyclic redundancy check (CRC), it is determined for each 8-bit word of the data block whether it is reliable or not. Tnis reliability indication per byte is necessary when use is made of an error correction algorithm which has a capability for error correction per word.
  • CRC cyclic redundancy check
  • Another well-defined 8-bit word is written at the memory address where the word in question would normally have been written.
  • Said other well-defined 8-bit word now acts as an unreliability indicator and will be so referred to hereinafter.
  • the same unreliability indicator is now used as a substitute for an unreliable word.
  • an exception word is selected.
  • An exception word is a word which is extremely rare or even absent in the data stream. The reasons for this will be discussed hereinafter.
  • the 8-bit word "1000 0000" is a suitable choice for the unreliability indicator. This is because this value corresponds to the full scale input range of the DA converter (digital-to-analog converter which translates the digital audio signal into an analog audio signal). However, this value will .only rarely occur in the audio data, because a very severe distortion due to clipping occurs when this range is overstepped.
  • Fig. 3 shows an embodiment of a device in accordance with the invention for substituting an unreliability indicator for unreliable words.
  • This device comprises an input register 1 having an output which is connected, via a bus 9, to a first input A of a selection unit 3, as well as to an input of a verifier 6.
  • a second input B of the selection unit is connected, via a bus, to output of a generator 2 for generating an unreliability indicator.
  • An output of the selection unit is connected to a memory 4, for example a RAM, which is the memory situated at the receiving side of the digital audio system.
  • the device is controlled by means of a data processor unit 5, for example a microprocessor.
  • the microprocessor and the verifier exchangecontrol data via a line 7.
  • the selection unit 3 is controlled on the one hand by the verifier which for this purpose is connected to the selection unit via the line 10, and on the other hand by the microprocessor which is connected to the selection unit via the line 12. Control data is transported on line 8 between the input register 1 and the microprocessor.
  • the memory 4 and microprocessor 5 communicate via the system bus 11 on which data and addresses are transported.
  • the data block in question is temporarily stored in the input register 1.
  • the microprocessor is informed that a data block has been stored in the input register.
  • the microprocessor then generates a first control signal which is applied, via the line 7, to the verifier 6 which is thus activated.
  • the verifier determines the redundancy from the data block and compares it with the added redundancy from the check bits forming part of the data block. When both redundancies correspond, the verified word is indicated as being a reliable word, or otherwise as an unreliable word.
  • the verifier Whilst the verifier checks the reliability of the words received as well as during the period during which no words originating from the input register are written into the memory 11, the input is connected to the output of the selection unit under the control of a second control signal which is generated by the microprocessor and which is applied to the selection unit via the line 12. Consequently, the output of the generator 2 is connected to a data input of the memory so that unreliability indicators are written into the memory.
  • the unreliability indicators are written in locations which succeed the last data word written and in which, moreover, no relevant data is present.
  • the microprocessor memorizes the position occupied by the address pointer at the instant at which the writing of unreliability indicators commences.
  • the writing of unreliability indicators is interrupted when the microprocessor is informed, via the line 7, that the verifier has completed its task for the data block received. Via a third control signal which is generated by the microprocessor, the input of the selection unit is uncoupled from the output.
  • the microprocessor memorizes at which addresses in the memory unreliability indicators have been written and sets the address pointer to the address as indicated by the address forming part of the data block presented.
  • the verifier has thus determined whether they are reliable or unreliable words.
  • the selection unit 3 is controlled by means of selection signals which are generated by the verifier and which are applied to the selection unit via the line 10.
  • the input Q9 is connected to the output of the selection unit. Consequently, the reliable word in question is written into the memory in the location indicated by the associated address.
  • the unreliability indicator already present in this location is erased by the reliable word.
  • the position 0 of the selection unit is chosen under the control of a selection signal from the verifier. In this position no new data is applied to the memory. Consequently, in the location where normally the unreliable word would have been written, the unreliability indicator already present remains.
  • the verifier can be made to generate a selection signal which switches the selection unit to the portion .
  • the first method is used. This is because this first method offers the advantage that, for example in the case of drop-outs or incorrect addressing, unreliability indicators are still written in the correct memory location.
  • Fig. 4 shows an embodiment of a device for reading and correcting data words from a memory in which an unreliability indicator is written irstead of unreliable words.
  • the memory 4, the generator 2, the microprocessor 5 and the bus 11 are identical to the corresponding components illustrated in fig. 3.
  • a first input of a comparison unit 20 is connected to the bus 11 whilst a second input is connected to an output of the generator 2 for an unreliability indicator.
  • Also connected to the bus 11 is a corrector 21, an interpolator 21 and a D/A (digital-to-analog)converter 24.
  • Each word read from the memory 4 is applied to the comparison unit 20 in order to be compared with the unreliability indicator generated by the generator 2. There are two possibilities:
  • the corrector attempts in known manner, for example by utilizing an algorithm, to produce a reliable word for the relevant unreliability indicator in order to write this reliable word into the memory instead of the unreliability indicator.
  • the corrector cannot successively perform this correction operation, the unreliability indicator remains in the memory.
  • the reliable data words are translated by the D/A converter into an analog audio signal which is outputted on an output 26.
  • any unreliability indicator in the data stream on the bus is detected by the comparison unit.
  • the comparison unit Upon detection of an unreliability indicator, the comparison unit generates a control pulse which is applied to the interpolator via the line 25. Under the control of this control pulse, the interpolator interpolates a substitute word for the unreliable word in known manner. The substitute word replaces the unreliability indicator in the data stream on the bus 11.
  • the D/A converter subsequently translates the substitute word in question into an analog audio signal.
  • the memory is preferably of the small outline package type (for example, HITACHI HM 6116 LFP).
  • Small outline package type memories are memories which occupy only little chip surface area. In addition to the saving of a separate flag bit memory, the use of a small outline package memory also saves an additional amount of chip surface area.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Multimedia (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
EP84201565A 1983-11-02 1984-10-31 Système de traitement de données dans lequel des mots non fiables de la mémoire sont remplacés par un indicateur de non-fiabilité Expired EP0140456B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8303765 1983-11-02
NL8303765A NL8303765A (nl) 1983-11-02 1983-11-02 Dataverwerkend systeem waarbij in het geheugen onbetrouwbare woorden zijn vervangen door een onbetrouwbaarheidsindicator.

Publications (2)

Publication Number Publication Date
EP0140456A1 true EP0140456A1 (fr) 1985-05-08
EP0140456B1 EP0140456B1 (fr) 1988-05-18

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EP84201565A Expired EP0140456B1 (fr) 1983-11-02 1984-10-31 Système de traitement de données dans lequel des mots non fiables de la mémoire sont remplacés par un indicateur de non-fiabilité

Country Status (7)

Country Link
US (1) US4641310A (fr)
EP (1) EP0140456B1 (fr)
JP (1) JPS60112149A (fr)
KR (1) KR930001587B1 (fr)
CA (1) CA1218747A (fr)
DE (1) DE3471383D1 (fr)
NL (1) NL8303765A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371593A2 (fr) * 1988-09-30 1990-06-06 Data General Corporation Méthode pour l'initialisation ou la synchronisation d'une ligne de communication
EP0414310A1 (fr) * 1989-08-24 1991-02-27 Koninklijke Philips Electronics N.V. Dispositif d'enregistrement et de lecture d'information, dispositif d'enregistrement d'information et support d'enregistrement obtenu à l'aide de l'un de ces dispositifs
EP0554858A2 (fr) * 1992-02-05 1993-08-11 Sony Corporation Appareil de lecture de disque et appareil d'enregistrement de disque

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247505A (en) * 1985-04-17 1993-09-21 Canon Kabushiki Kaisha Information recording method for reciprocally recording and verifying information
JPH0654590B2 (ja) * 1985-07-24 1994-07-20 パイオニア株式会社 ディジタルデータの再生方法
JPS6246347A (ja) * 1985-08-24 1987-02-28 Hitachi Ltd 情報処理装置のエラ−処理方式
US4698812A (en) * 1986-03-03 1987-10-06 Unisys Corporation Memory system employing a zero DC power gate array for error correction
US4719627A (en) * 1986-03-03 1988-01-12 Unisys Corporation Memory system employing a low DC power gate array for error correction
US4817095A (en) * 1987-05-15 1989-03-28 Digital Equipment Corporation Byte write error code method and apparatus
US5020081A (en) * 1988-09-30 1991-05-28 Data General Corporation Communication link interface with different clock rate tolerance
US5070502A (en) * 1989-06-23 1991-12-03 Digital Equipment Corporation Defect tolerant set associative cache
JPH081755B2 (ja) * 1989-06-26 1996-01-10 日本電気株式会社 置換アドレス判定回路
KR920005291B1 (ko) * 1990-08-09 1992-06-29 삼성전자주식회사 Cd-rom의 삭제 비트 저장방법 및 회로
MY109399A (en) * 1992-01-07 1997-01-31 Koninklijke Philips Electronics Nv Device for processing digital data, and digital video system comprising the device
US5473753A (en) * 1992-10-30 1995-12-05 Intel Corporation Method of managing defects in flash disk memories
US20060077750A1 (en) * 2004-10-07 2006-04-13 Dell Products L.P. System and method for error detection in a redundant memory system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585619A (en) * 1969-01-14 1971-06-15 Mohawk Data Sciences Corp Magnetic tape readout system with means to generate artificial signals
US3688261A (en) * 1970-10-05 1972-08-29 Litton Business Systems Inc Logic processing system
JPS5647908A (en) * 1979-09-21 1981-04-30 Nec Corp Magnetic tape processor
JPS573209A (en) * 1980-06-05 1982-01-08 Nec Corp Control system for magnetic tape device
EP0086658A2 (fr) * 1982-02-15 1983-08-24 Sony Corporation Appareil de correction de base de temps

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768071A (en) * 1972-01-24 1973-10-23 Ibm Compensation for defective storage positions
US3780271A (en) * 1972-09-29 1973-12-18 Sigma Systems Error checking code and apparatus for an optical reader
US3836957A (en) * 1973-06-26 1974-09-17 Ibm Data storage system with deferred error detection
US4037091A (en) * 1976-04-05 1977-07-19 Bell Telephone Laboratories, Incorporated Error correction circuit utilizing multiple parity bits
US4072853A (en) * 1976-09-29 1978-02-07 Honeywell Information Systems Inc. Apparatus and method for storing parity encoded data from a plurality of input/output sources
JPS5735444A (en) * 1980-08-12 1982-02-26 Sony Corp Pcm signal transmission method
US4434487A (en) * 1981-10-05 1984-02-28 Digital Equipment Corporation Disk format for secondary storage system
US4458349A (en) * 1982-06-16 1984-07-03 International Business Machines Corporation Method for storing data words in fault tolerant memory to recover uncorrectable errors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585619A (en) * 1969-01-14 1971-06-15 Mohawk Data Sciences Corp Magnetic tape readout system with means to generate artificial signals
US3688261A (en) * 1970-10-05 1972-08-29 Litton Business Systems Inc Logic processing system
JPS5647908A (en) * 1979-09-21 1981-04-30 Nec Corp Magnetic tape processor
JPS573209A (en) * 1980-06-05 1982-01-08 Nec Corp Control system for magnetic tape device
EP0086658A2 (fr) * 1982-02-15 1983-08-24 Sony Corporation Appareil de correction de base de temps

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 5, no. 101 *
PATENT ABSTRACTS OF JAPAN vol. 6, no. 62 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371593A2 (fr) * 1988-09-30 1990-06-06 Data General Corporation Méthode pour l'initialisation ou la synchronisation d'une ligne de communication
EP0371593A3 (fr) * 1988-09-30 1991-07-17 Data General Corporation Méthode pour l'initialisation ou la synchronisation d'une ligne de communication
EP0414310A1 (fr) * 1989-08-24 1991-02-27 Koninklijke Philips Electronics N.V. Dispositif d'enregistrement et de lecture d'information, dispositif d'enregistrement d'information et support d'enregistrement obtenu à l'aide de l'un de ces dispositifs
EP0554858A2 (fr) * 1992-02-05 1993-08-11 Sony Corporation Appareil de lecture de disque et appareil d'enregistrement de disque
EP0554858A3 (en) * 1992-02-05 1994-11-30 Sony Corp Disc reproducing apparatus and disc recording apparatus
US5410526A (en) * 1992-02-05 1995-04-25 Sony Corporation Disc reproducing apparatus and disc recording apparatus

Also Published As

Publication number Publication date
EP0140456B1 (fr) 1988-05-18
US4641310A (en) 1987-02-03
KR930001587B1 (ko) 1993-03-05
CA1218747A (fr) 1987-03-03
DE3471383D1 (en) 1988-06-23
NL8303765A (nl) 1985-06-03
JPS60112149A (ja) 1985-06-18
KR850003602A (ko) 1985-06-20

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