EP0136174B1 - Hardware für Arithmetik-Logikeinheitsprüfung - Google Patents

Hardware für Arithmetik-Logikeinheitsprüfung Download PDF

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Publication number
EP0136174B1
EP0136174B1 EP84306547A EP84306547A EP0136174B1 EP 0136174 B1 EP0136174 B1 EP 0136174B1 EP 84306547 A EP84306547 A EP 84306547A EP 84306547 A EP84306547 A EP 84306547A EP 0136174 B1 EP0136174 B1 EP 0136174B1
Authority
EP
European Patent Office
Prior art keywords
inputs
input
arithmetic logic
alu
logic unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP84306547A
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English (en)
French (fr)
Other versions
EP0136174A2 (de
EP0136174A3 (en
Inventor
Robert Whiting Horst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
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Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Publication of EP0136174A2 publication Critical patent/EP0136174A2/de
Publication of EP0136174A3 publication Critical patent/EP0136174A3/en
Application granted granted Critical
Publication of EP0136174B1 publication Critical patent/EP0136174B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2226—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test ALU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Definitions

  • the present invention relates to central processing units (CPUs) in data processing systems. More particularly, the invention relates to the arithmetic logic units (ALUs) contained within CPUs in data processing systems and conditions which may be tested for by software with respect to the data presented to ALUs.
  • CPUs central processing units
  • ALUs arithmetic logic units
  • ALU typically has two inputs to which operands are presensed and upon which the ALU performs one of several arithmetic or logical functions.
  • the ALU "result" is the quantity which is presented at the output of the ALU as a result of the particular arithmetic or logical function which the ALU has been instructed by software to perform on the input operands.
  • This test examines the output of the ALU to determine whether in fact the ALU output is equal to zero.
  • This test has assumed more than one form.
  • the test allows masking of a subset of the bits forming one input to the ALU to ascertain whether a given bit field portion appearing on the other ALU input is equal to zero.
  • a chosen portion of one input to the ALU is set with all logical "ones" while all other portions of the bit field of that input are "masked” or set to logical "zero".
  • Another common use of this test is a loop counter routine wherein one input to the ALU is a value which is decremented in a subtract operation by the value placed on the other input to the ALU. After each decrement operation, the ALU result is tested to see if it is equal to zero. When the result is equal to zero, the loop counter routine is terminated.
  • IBM Technical Disclosure Bulletin, Vol. 24, No. 8, of January 1982; p. 4410 discusses a system in which there is a test capability outside the data flow.
  • the test for the condition code is performed at the input, and therefore this document discloses an apparatus for performing one or more tests on data presented to the inputs of an arithmetic logic unit in a central processing unit of a data processing system, with the arithmetic logic having two inputs.
  • Data inputs, representative of first and second desired quantities, are provided to first and second inputs, and a subtract operation performed. This document thus discloses the features of the pre-characterising part of claims 1 and 5.
  • the present invention therefore seeks to provide the CPU user with a set of tests which are in most cases the functional equivalent of the currently employed ALU result test but which do not require a time delay while the ALU performs its function and a further time delay while the test is performed on the ALU result.
  • the present invention also seeks to provide testing for the equivalent of the results of an ALU operation which does not require the use of hardware on the output of an ALU.
  • the present invention further seeks to provide testing for the equivalent of the results of an ALU operation which leaves the ALU free to perform a different operation on the same operands.
  • the apparatus has:
  • the method of operating includes the steps of:
  • a comparator connected to both inputs of the ALU performs a bit-for-bit comparison of the values placed on the inputs to the ALU to determine if the value on input A is equal to the value on input B.
  • a microcode mask is placed on one of the inputs to the ALU and the entire contents of that input are ANDed with the entire contents of the other input on a bit-for-bit basis.
  • the bit-for-bit results are presented to an NOR gate whose output indicates whether the one bus ANDed with the other bus gives a zero result.
  • Arithmetic logic unit (ALU) 10 is shown having two inputs, A input 12 and B input 14.
  • ALU 10 also has output lines 16 on which the results of the arithmetic or logical operation performed on A and B are presented. It will be understood by those of ordinary skill in the art, that both inputs A and B and output 16 may comprise N lines, where N is the word size operated on by the processor.
  • a input 12 and B input 14 to the ALU are also connected as inputs to compare circuit 18.
  • Compare circuit 18 performs a bit-by-bit comparison of the corresponding bits on input line A 12 and input line B 14.
  • Compare circuit 18 delivers a logical one output on output line 20 if all the bits of A input 12 equal all the bits of B input 14.
  • Mask and zero detect unit 22 is also connected to A input 12 and B input 14 of ALU 10.
  • the function of mask and zero detect unit 22 is to determine whether the contents of A input 12 and B input 14, when logically ANDed together, equal zero. Selective bit field masking may be performed on either all or part of the contents of either A input 12 or B input 14 by microcode as is known in the art. If the logical AND product of A input 12 and B input 14 is zero, a logic one will appear at the output 24 of mask and zero detect unit 22.
  • Another ALU output test which is replaced by the tests disclosed herein involves masking a subset of bits on one ALU input to determine if a chosen partial bit field of that input is equal to zero.
  • a mask was placed on one ALU input the data to be tested was placed on the other input, and the ALU was instructed to perform a logical AND operation. The ALU result was then tested to see if it equalled zero.
  • the same bits are masked on one ALU input and the zero detecting unit 22 performs the functional equivalent of this test on the ALU input, thus making the result available for use earlier in the CPU cycle.
  • Exclusive OR gate 50 has one of its inputs 52 connected to the least significant bit AO of the A input 12 to ALU 10, and its other input 54 connected to the least significant bit of the B input 14 to ALU 10. Its output 56 is presented to NOR gate 58.
  • exclusive OR gate 60 has its one input 62 connected to the most significant bit of A input 12 of ALU 10 and its other input 64 connected to the most significant bit Bn of B input 14 to ALU 10. Its output 66 is likewise connected to an input of NOR gate 58.
  • the other corresponding bits of both A input 12'and B input 14 to ALU 10 are connected to exclusive OR gates (not shown) whose outputs are connected to other inputs to NOR gate 58. These inputs are shown generally at 68.
  • AND gate 100 has one of its inputs 102 connected to least significant bitAO of A input 12 to ALU 10. Its other input 104 is connected to least significant bit BO of B input 14to ALU 12. The output of AND gate 100 at 106 is presented to NOR gate 108.
  • AND gate 110 has one of its inputs 112 connected to most significant bit An of A input 12 to ALU 10 its other input 114 connected to most significant bit Bn of B input 14to ALU 10. The output 116 of AND gate 110 is also connected to an input of NOR gate 108.
  • corresponding A and B bits are presented to the inputs of other AND gates (not shown) whose outputs are also connected to the inputs of NOR gate 108. These inputs are shown generally at 118.
  • output 120 of NOR gate 108 will only be at a logic one if all of its inputs are zero, i.e., if none of the AND gates 100 or 110, have both of their inputs at a logic one level.

Claims (5)

1. Vorrichtung zur Durchführung einer oder mehrerer Prüfungen an Daten, die den Eingängen einer Arithmetik-Logikeinheit in einer zentralen Datenverarbeitungseinheit eines Datenverarbeitungssystems eingegeben werden, welche genannte Arithmetik-Logikeinheit zwei Eingänge aufweist, gekennzeichnet durch:
eine Einrichtung, die direkt mit den beiden Eingängen der genannten Arithmetik-Logikeinheit gekoppelt ist, um zu prüfen, ob die den beiden genannten Eingängen eingebenen genannten Daten gleich sind; und durch
eine Einrichtung, die direkt mit den beiden Eingängen der genannten Arithmetik-Logikeinheit gekoppelt ist, um zu prüfen, ob das logische UND-Produkt der genannten Daten, die den beiden genannten Eingängen eingegeben werden, gleich Null ist.
2. Vorrichtung nach Anspruch 1, worin die Prüfungen während der gleichen Taktzeit vorgenommen werden die der Betrieb der genannten Arithmetik-Logikeinheit der genannten zentralen Verarbeitungseinheit.
3. Vorrichtung nach Anspruch 2, worin die genannte Einrichtung, um zu prüfen, ob die genannten Daten an den beiden genannten Eingängen gleich sind, dazu ausgebildet ist, ein erstes Signal zu erzeugen, so daß das genannte erste Signal einen ersten Zustand annimmt, wenn die genannten Daten an den beiden genannten Eingängen gleich sind und einen zweiten Zustand annimmt, wenn die genannten Daten an den genannten beiden Eingängen nicht gleich sind.
4. Vorrichtung nach Anspruch 3, worin die genannte Einrichtung, um zu prüfen, ob das logische UND-Produkt der genannten Daten an den beiden genannten Eingängen gleich Null ist, dazu ausgebildet ist, ein zweites Signal zu erzeugen, sodaß das zweite Signal einen ersten Zustand annimmt, wenn das genannten UND-Produkt gleich Null ist und einen zweiten Zustand annimmt, wenn das genannten UND-Produkt ungleich Null ist.
5. Verfahren zum Betrieb eines Schleifenzählprogramms in einer zentralen Verarbeitungseinheit eines Digitalrechners, das Verfahren umfassend die Schritte:
a) Eingeben einer Dateneingabe, die einer ersten gewünschten Größe entspricht, einem ersten Eingang einer Arithmetik-Logikeinheit,
b) Eingeben einer Dateneingabe, die einer zweiten gewünschten Größe entspricht, einem zweiten Eingang der genannten Arithmetik-Logikeinheit,
c) Durchführen einer Subtraktionsoperation unter Verwendung der genannten Arithmetik-Logikeinheit während eines ersten Taktzeitraums;
dadurch gekennzeichnet, daß das Verfahren weiters die Schritte umfaßt:
d) Durchführung einer Äquivalenzprüfung an den genannten ersten und zweiten Eingängen der Arithmetik-Logikeinheit außerhalb der genannten Arithmetik-Logikeinheit während des genannten ersten Taktzeitraums und
e) Abbruch bzw. Beendigung des genannten Schleifenzählprogramms, falls das Ergebnis der genannten Äquivalenzprüfung anzeigt, daß der erste und zweite Eingang der Arithmetik-Logikeinheit gleich sind und Rückführung der Ergebnisse der genannten Subtraktionsoperation der genannten Arithmetik-Logikeinheit an den genannten ersten Eingang der genannten Arithmetik-Logikeinheit, wenn das Ergebnis der genannten Äquivalenzprüfung anzeigt, daß die genannten ersten und zweiten Eingänge der Arithmetik-Logikeinheit nicht gleich sind.
EP84306547A 1983-09-29 1984-09-26 Hardware für Arithmetik-Logikeinheitsprüfung Expired EP0136174B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/537,041 US4618956A (en) 1983-09-29 1983-09-29 Method of operating enhanced alu test hardware
US537041 1983-09-29

Publications (3)

Publication Number Publication Date
EP0136174A2 EP0136174A2 (de) 1985-04-03
EP0136174A3 EP0136174A3 (en) 1987-07-01
EP0136174B1 true EP0136174B1 (de) 1989-12-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP84306547A Expired EP0136174B1 (de) 1983-09-29 1984-09-26 Hardware für Arithmetik-Logikeinheitsprüfung

Country Status (7)

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US (1) US4618956A (de)
EP (1) EP0136174B1 (de)
JP (1) JPS60168243A (de)
AU (1) AU566813B2 (de)
CA (1) CA1216070A (de)
DE (1) DE3480743D1 (de)
NO (1) NO843897L (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611934B2 (en) 1988-09-07 2003-08-26 Texas Instruments Incorporated Boundary scan test cell circuit
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6727722B2 (en) 1995-10-31 2004-04-27 Texas Instruments Incorporated Process of testing a semiconductor wafer of IC dies
US6763485B2 (en) 1998-02-25 2004-07-13 Texas Instruments Incorporated Position independent testing of circuits
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter

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Publication number Priority date Publication date Assignee Title
US4800486A (en) * 1983-09-29 1989-01-24 Tandem Computers Incorporated Multiple data patch CPU architecture
US4747046A (en) * 1985-06-28 1988-05-24 Hewlett-Packard Company Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch
EP0358371B1 (de) * 1988-09-07 1998-03-11 Texas Instruments Incorporated Erweiterte Prüfschaltung
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
DE4334294C1 (de) * 1993-10-08 1995-04-20 Ibm Prozessor für Zeichenketten variabler Länge
JPH09231896A (ja) * 1996-02-20 1997-09-05 Nec Corp シーソー式電磁継電器
US6035390A (en) * 1998-01-12 2000-03-07 International Business Machines Corporation Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
GB2342729B (en) * 1998-06-10 2003-03-12 Lsi Logic Corp Zero detection in digital processing
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US7600161B2 (en) * 2004-08-13 2009-10-06 Gm Global Technology Operations, Inc. Method of verifying integrity of control module arithmetic logic unit (ALU)
CN103513177B (zh) * 2012-06-29 2018-05-01 上海芯豪微电子有限公司 运算器测试系统及测试方法

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US3931505A (en) * 1974-03-13 1976-01-06 Bell Telephone Laboratories, Incorporated Program controlled data processor
US3988670A (en) * 1975-04-15 1976-10-26 The United States Of America As Represented By The Secretary Of The Navy Automatic testing of digital logic systems
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611934B2 (en) 1988-09-07 2003-08-26 Texas Instruments Incorporated Boundary scan test cell circuit
US6813738B2 (en) 1988-09-07 2004-11-02 Texas Instruments Incorporated IC test cell with memory output connected to input multiplexer
US6727722B2 (en) 1995-10-31 2004-04-27 Texas Instruments Incorporated Process of testing a semiconductor wafer of IC dies
US6763485B2 (en) 1998-02-25 2004-07-13 Texas Instruments Incorporated Position independent testing of circuits
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter

Also Published As

Publication number Publication date
DE3480743D1 (de) 1990-01-18
AU566813B2 (en) 1987-10-29
AU3359084A (en) 1985-04-04
CA1216070A (en) 1986-12-30
JPS60168243A (ja) 1985-08-31
US4618956A (en) 1986-10-21
EP0136174A2 (de) 1985-04-03
EP0136174A3 (en) 1987-07-01
NO843897L (no) 1985-04-01

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