GB2342729B - Zero detection in digital processing - Google Patents

Zero detection in digital processing

Info

Publication number
GB2342729B
GB2342729B GB9812505A GB9812505A GB2342729B GB 2342729 B GB2342729 B GB 2342729B GB 9812505 A GB9812505 A GB 9812505A GB 9812505 A GB9812505 A GB 9812505A GB 2342729 B GB2342729 B GB 2342729B
Authority
GB
United Kingdom
Prior art keywords
digital processing
zero detection
zero
detection
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9812505A
Other versions
GB2342729A (en
GB9812505D0 (en
Inventor
Kar Lik Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Priority to GB9812505A priority Critical patent/GB2342729B/en
Publication of GB9812505D0 publication Critical patent/GB9812505D0/en
Priority to US09/328,335 priority patent/US6424955B1/en
Publication of GB2342729A publication Critical patent/GB2342729A/en
Application granted granted Critical
Publication of GB2342729B publication Critical patent/GB2342729B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
GB9812505A 1998-06-10 1998-06-10 Zero detection in digital processing Expired - Fee Related GB2342729B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9812505A GB2342729B (en) 1998-06-10 1998-06-10 Zero detection in digital processing
US09/328,335 US6424955B1 (en) 1998-06-10 1999-06-09 Zero detection in digital processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9812505A GB2342729B (en) 1998-06-10 1998-06-10 Zero detection in digital processing

Publications (3)

Publication Number Publication Date
GB9812505D0 GB9812505D0 (en) 1998-08-05
GB2342729A GB2342729A (en) 2000-04-19
GB2342729B true GB2342729B (en) 2003-03-12

Family

ID=10833521

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9812505A Expired - Fee Related GB2342729B (en) 1998-06-10 1998-06-10 Zero detection in digital processing

Country Status (2)

Country Link
US (1) US6424955B1 (en)
GB (1) GB2342729B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7047272B2 (en) * 1998-10-06 2006-05-16 Texas Instruments Incorporated Rounding mechanisms in processors
WO2007085914A1 (en) * 2006-01-27 2007-08-02 Freescale Semiconductor, Inc. Device and method for adding and subtracting two variables and a constant
US8015230B2 (en) * 2007-06-08 2011-09-06 Apple Inc. Fast modular zero sum and ones sum determination
US20090292757A1 (en) * 2008-05-23 2009-11-26 Steven Leeland Method and apparatus for zero prediction
US10101967B2 (en) * 2017-02-22 2018-10-16 International Business Machines Corporation Zero detection of a sum of inputs without performing an addition

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4618956A (en) * 1983-09-29 1986-10-21 Tandem Computers Incorporated Method of operating enhanced alu test hardware
US5367477A (en) * 1993-11-29 1994-11-22 Motorola, Inc. Method and apparatus for performing parallel zero detection in a data processing system
WO1996010784A1 (en) * 1994-09-30 1996-04-11 Vlsi Technology, Inc. Arithmetic logic unit with zero sum prediction
US5561619A (en) * 1993-12-27 1996-10-01 Fujitsu Limited Arithmetic logic unit provided with combinational circuit and zero value detector connected in parallel
US5581496A (en) * 1992-07-20 1996-12-03 Industrial Technology Research Institute Zero-flag generator for adder
US5862065A (en) * 1997-02-13 1999-01-19 Advanced Micro Devices, Inc. Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
JPH01277931A (en) * 1988-04-29 1989-11-08 Nec Ic Microcomput Syst Ltd Zero detecting circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4618956A (en) * 1983-09-29 1986-10-21 Tandem Computers Incorporated Method of operating enhanced alu test hardware
US5581496A (en) * 1992-07-20 1996-12-03 Industrial Technology Research Institute Zero-flag generator for adder
US5367477A (en) * 1993-11-29 1994-11-22 Motorola, Inc. Method and apparatus for performing parallel zero detection in a data processing system
US5561619A (en) * 1993-12-27 1996-10-01 Fujitsu Limited Arithmetic logic unit provided with combinational circuit and zero value detector connected in parallel
WO1996010784A1 (en) * 1994-09-30 1996-04-11 Vlsi Technology, Inc. Arithmetic logic unit with zero sum prediction
US5862065A (en) * 1997-02-13 1999-01-19 Advanced Micro Devices, Inc. Method and circuit for fast generation of zero flag condition code in a microprocessor-based computer

Also Published As

Publication number Publication date
GB2342729A (en) 2000-04-19
US6424955B1 (en) 2002-07-23
GB9812505D0 (en) 1998-08-05

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20150610