Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N7/00—Television systems
  • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
  • H04N7/083—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical and the horizontal blanking interval, e.g. MAC data signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N11/00—Colour television systems
  • H04N11/06—Transmission systems characterised by the manner in which the individual colour picture signal components are combined
  • H04N11/08—Transmission systems characterised by the manner in which the individual colour picture signal components are combined using sequential signals only
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/44—Colour synchronisation

Definitions

• the present invention relates * to a system for transmitting and/or receiving television video signals in component form, which components have been time compressed and placed sequentially so as to occupy, together with the necessary sync and clamping signals, a period substantially identical to the existing line period e.g. approximately 64 IAS.
• this audio signal takes the form of a digital signal placed before the video components signals. Further, it has been proposed to add to this digital signal a predetermined sequence of digits for use as either a sound or line sync signal.
• OMPI be repeated for a plurality of lines at the beginning of the next field. The sequences will then alternate as before.
• the present invention provides apparatus for deriving synchronisation signals from a received television signal which has a sequence of a plurality of different digital words; each is a respective one of a plurality of lines as synchronisation signals, comprising means for generating a " first sxgnal indicative of detection of one of the digital words, means for generating a further signal indicative of detection of a further digital word, means for evaluating the first and further signals to determine the sequence and timing of the first and further signals whereby to generate a signal indicative of synchronisation signal acquisition for initiating generating of receiver sync signals at line frequency.
• Figure 1 shows diagrammatically a multiplexed component signal showing the time division multiplex between the component parts thereof;
• Figure 2 shows diagrammatically a frame of C-MAC signals offset by _ frame and _ line as well as the multiple timing of each line in the frame .
• FIG. 3 shows a block diagram of a receiver incorporating the present invention
• Figure 4 shows a state diagram to explain the operation of the circuit shown in Figure 3-
• Figure 5 shows a block diagram of a further receiver incorporating the present invention.
• Figures 6A and 6B show state diagrams to explain the operation of the circuit shown in Figure 5- - 3 -
• the Multiplex Analogue Components (MAC) system for whom television signal transmission replaces the colour subcarrier coding of NTSC, PAL and SECAM with a single method of time compression.
• the conventional MAC Multiplex Analogue Components
• This time compression results in a proportionate 20 increase in the bandwidth required to pass the signal.
• the extra bandwidth of the time-compressed baseband signal can be accommodated within a satellite FM transmission channel, since the spectral width of the FM signal is a function of both the frequency and 25 amplitude of the baseband signals.
• the synchronisation, sound and data signals are digitally modulated onto the carrier in the line-blanking interval of the MAC signal, giving an overall time division 30 multiplex of the RF carrier as shown in Fig 1.
• the complete absence of high frequency sub-carriers either for colour or for sound allows the bandwidth of the baseband signals to be increased with the upper limit set by interference constraints.
• OMPI subcarriers becomes unnecessary.
• the pre- and de-emphasis can be reduced to a level to give optimum noise and interference performance.
• Time division multiplexing of the digital synchronisation, sound and data with the analogue video signal is carried out at an intermediate frequency, switching between digital modulation for the synch ⁇ ronisation, sound and data, and frequency modulation for the chrominance and luminance as shown in Figure 1. Such switching is carried our without discontinuity of phase in the main carrier.
• the same data rate is chosen for the sound signal.
• Synchronisation signals for C-MAC are: i) video line sync ii) video frame sync iii) U/V identification iv) Extended-definition synchronisation v) Sound synchronisation
• Video line sync This is available in two ways.
• the first 8 bits of the digital burst carry synchronisation information, consisting of a run-in bit for differential detection and seven bits for the synchronising words .
• synchronisation information consisting of a run-in bit for differential detection and seven bits for the synchronising words .
• W.. and Wtile which are sent on alternate lines. Their relative positions are inverted once every frame to provide a frame reference as shown in Table 2 belbw.
• Line syncs may also be derived by detecting a unique frame sync word placed in line 625 as shown in 35 Fig. 2 and using this to lock an oscillator running at line rate.
• OMPI b From the video waveform. This is provided by the exact spacing of edges 'e' and 'h' of Figure (2). Edges which may occur in pictures at the same spacing are eliminated by the field sync lines in which there is no picture information. The amplitude of the sync edges (0.5v) allows for rugged sync separation.
• Video field sync This is available in two ways.
• the first 8 bits of the digital burst provide not only the line syncs, but by inversion of the relative positions of the words once every frame a rugged frame sync is provided as shown in Table 2 above.
• a distinct and unique field sync word can be inserted in line 625 as shown in Fig. 2.
• Line 1 of the video consists of the waveform shown in Figure 9 while line 313 contains the wave ⁇ form shown in Figure 10. This provides a very rugged method of frame synchronis ⁇ ation, since these lines are clearly distinguishable from any other line of each frame.
• Sound synchronisation is obtained by obtaining line and frame synchronisation from the digital burst which then provides total synchronisation of the sound/data channel.
• timings for the MAC receiver are derived from a line-locked 20.25MHz clock. This has a period of ⁇ >49 S, and there are 1296 clock samples per television line. As timing information for clock regeneration is derived from the data burst, it can be seen that timing information is only present for 15 of the time.
• the synchronisation period consists of an 8-bit sequence transmitted at the start of each data burst. Of this the first bit is a run-in bit, and without synchronisation detection can be considered to be of no useful value.
• the other seven bits contain both the horizontal and vertical sync information in the format shown below.
• a frame sync will then consist of the sequences .
• Both W. and W 2 should be chosen to have smallest possible correlation with shifted versions of themselves to prevent false lock occuring. Based on computer search, the seven bit sequence 0001101 has been found to be optimum with regard to shifted versions of itself and also simulation of the sequence by video/data and noise.
• W 2 was chosen to be 1110010.
• the run in bit was chosen to be 1 for W.. and 0 for W 2 .
• W 2 Although only seven bits of sync information are sent on each line, the sequence of W. W 2 allows an effective line sync word length of 14 bits and an effective frame sync word length of 28 bits to be used. This is shown below:-
• a line sync is therefore present on every line and a frame sync once a frame.
• the line marked ! contains a valid line sync, but the W 1 W 2 pair sequence is inverted. This can be used as a less rugged form of frame sync if desired for a simpler receiver and is indicated in Fig. 2.
• a phase locked loop recovers the 20.25MHz clock from the incoming data stream in a con ⁇ ventional manner. Even when not locked, the oscilllator of the phase locked loop is running at a nominal 20.25MHz and so there is only scale difference in phase between the incoming data stream and the oscillator which results in long period of in phase running of the oscillator in facilitate lock-up.
• the figure -2-jfc may be used as a measure of the BER for the channel.
• This operation is achieved by means of an inverter 22 which inverts the present sample and feeds it to one input of an adder 23 whose other input is supplied with the output from a line delay circuit 24.
• the output of the adder 23 is fed to a comparing circuit 25 where the 4 bit output of the adder 23 is compared with predetermined maximum and minimum numbers of errors and if the level of the output of the adder 23 falls between the maximum and minimum numbers of errors a line sync detection signal is generated.
• a frame sync signal could also be extracted from the circuit 25 by detection when minimum and maximum signals are produced.
• the uninverted present sample is in this case summed with the same sample from the previous line in an adder 27- This gives a minimum for W. . and a maximum for the sequence W 2 W 2 .
• This result is delayed by two lines in a delay circuit 28 which comprises a 2 x 4 bit 2 line gated latch and added to the inverted undelayed signal 0 in an adder 30.
• False sync pulses may also be Q generated by the random data in the channel, or by a particular arrangement of video signals. Therefore some sort of discrimination is required to extract the true syncs from any possible misdetections.
• the counter progresses to - state 4 and the system has aquired lock.
• Sync acquisition is thus by two distinct processes : 1) Detection of line and frame sync. 2) Lock acquisition and digital flywheeling. Clock recovery is gated as soon as line lock is established (3 lines) thereby reducing clock jitter at low C/N. The clock has only to run ungated for 3 lines as opposed to running ungated accurately for at least one frame.
• Figure 5 shows a block diagram of a part of a receiver concentrating on sync detection and acquisition which differs from that shown in Fig. 3 in that it is much more simple and easy to instruct.
• the previously described receiver required a
• OMPI fairly substantial amount of hardware, mostly running at the 20.25Mb/s clock rate.
• the receiver shown in Figure 5 and described below has a considerably reduced amount of logic running at 20.25MHz and in particular contains no line store.
• the same reference numerals are used for the same parts as in Fig. 3>
• a line sync acquisition and flywheel and state counter circuit 41 receives an input from a word detection circuit each time a j or W 2 word is detected by a word detection circuit 4 connected to the output of the circuit 40. It also receives the line sync detection signal generated by the comparing circuit 25-
• the counter circuit 41 generates a number of outputs among which is a line rate clock signal which is fed to a 3-bit latch 43 which replaces the line delay circuit 24 of Fig. 3.
• the counter circuit 41 also acts as a reference signal generator for generating reference signals for application to a word detector and adaptive error control circuit 44j the reference signal being used to select the type of detection and number of errors tolerated by the detector 2 and the comparing circuit 25-
• Frame syncs are detected using a 2 latch double line delay as before, and frame lock is also acquired as before.
• increasing BER will increase the probability of sync detection being missed and hence the counters 41 and 46 will advance from the in lock state.
• the number of errors tolerated before a sync word detection is missed is increased using the circuits 44 and 47, therefore giving a greater probability of detecting a sync word in the presence of noise.
• Adaptive error tolerance on either or both line and frame sync detection allows sync extraction in the presence of a greater amount of noise (or higher BER) .
• the arrangement shown in Fig. 5 has an increased initial lock up time with respect to that of Fig. 3- This is increased by an average of 1 _ lines in low BER conditions o approximately 40 lines at a BER of 10 " .

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Television Systems (AREA)

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• 1983
  • 1983-12-02 WO PCT/GB1983/000315 patent/WO1984002242A1/en active IP Right Grant
  • 1983-12-02 EP EP84900082A patent/EP0126759B1/de not_active Expired
  • 1983-12-02 DE DE8484900082T patent/DE3381927D1/de not_active Expired - Lifetime
  • 1983-12-02 JP JP84500105A patent/JPS59502167A/ja active Pending
  • 1983-12-02 AT AT84900082T patent/ATE57289T1/de not_active IP Right Cessation

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