GB2245727A - Method and apparatus for generating timing signals - Google Patents

Abstract

The timing signal generator includes a memory 24 containing a sequence of bit patterns and associated timing interval data. An address counter 30 selects each bit pattern and associated timing interval in turn from the sequence. The bit pattern is loaded into an output latch 40 and the timing interval is loaded into a countdown timer 44. The bit pattern states are provided as a plurality of output signals 43 for a time interval determined by the countdown timer. The final bit pattern in the sequence is encoded with a "frame end" bit which is detected to control the address counter to repeat the selection of bit patterns from the sequence when the end of the sequence is reached. The generator outputs a set of continuous periodic wave forms. <IMAGE>

Description

MEISOD AND APPARATUS FOR GENERATING TIMING SIGNALS FIElD OF THE INVENTION The present invention relates to the generation of timing signals, and in particular to a digital technique for generating a plurality of periodic timing signals.

BACKGROUND OF A timing signal is a train of pulses at predefined intervals.

Conventional timing generators are generally based on state-machines or sequence counters. Using either of these tends to be inflexible as the set of timing signals are defined when the hardwaz-e is assembled.

SUMMERY OF THE INVENTION The present invention is defined in the appended claims.

The principle of the invention is to encode the set of timing signals as a sequence of bit patterns and associated timing information. Each bit pattern represents the digital state of an instantaneous set of output signals, and the timing information represents the interval or duration for which the output signals remain in that state.

This technique is very similar to run length encoding, applied to the set of output signals with the timing information corresponding to the run-length portion of the encoded signal.

Once encoded, the pairs of bit pattern and timing information data can be stored in a memory.

To generate the set of timing signals, the bit pattern data and the timing information data is provided in sequence, and an output corresponding to each bit pattern is provided for a time interval determined by the associated information.

At the end of the sequence, the sequence is restarted at the initial bit pattern, thereby providing a continuous periodic output.

A timing signal generator in accordance with this invention includes means for providing a sequence of bit patterns and associated timing information, and means for providing a set of output signals corresponding to each bit pattern in sequence, for a time interval determined by the associated timing information.

The providing means preferably comprises a memory containing the encoded data, and means for reading the data from the memory. The reading means can e.g. be a sequential mEmory address counter.

with this technique, a generator Cdfl be built to a standard hardaare design, and the set of timing signals be determined by code stored in a memory. The timing signals can be redefined by writing new data to the memory, or alternatively another section of memory can accessed with the alternative code. This enables a generator to be programmable to generate any selected one of pre-programmed timing signals, e.g. either PAL or NTSC timing signals for television or graphics signal processing.

In a preferred embodiment, a timing signal generator comprises: memory means adapted to store a plurality of run length encoded instructions, each said instruction including a run-length portion, a bit pattern portion and a frame end bit; address counter means adapted to sequentially select said instructions wherein said bit pattern is loaded to an output latch and said run length is loaded into a down counter; each said bit pattern being held at said output latch until the corresponding run length is decremented to zero by a master clock signal, wherein the next sequential instruction is selected; and testing means adapted to test said frame end bit when said bit is set, reset said counter to a base one of said instructions.

DESCRIPTION OF THE DRAWINGS An embodiment of the invention will now be described by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a timing signal generator; and Fig. 2 is bit-map showing the organisation of data in the memory of the generator.

DESCRIPTIQN OF A PREFERRED EMBODIMENT The timing generator shown in Fig. 1 comprises a first section 20 which forms providing means for providing a sequence of encoded data representing a plurality of timing signals to be generated, a second section 21 for selecting portions of the squence in turn, and a third section 22 for providing the output signals from the selected portions of encoded data.

The providing means 20 comprises a data memory 24 organised as two pages, and a page selector 26 for selecting the page of memory to be accessed. The page selector has an input MapWr 28 for controlling which page is selected.

The selecting means 20 includes an address counter 30 coupled to the memory 24 by an address bus 31. The counter 30 generates a sequence of addresses to access a predetermined sequence of the encoded data from the memory 24. The address counter 30 is controlled by a next run input 34 and a start sequence input 36. When a Next Run signal is applied to the next run input 34, this causes the address value in the counter 30 to be incremented to access the next set of encoded data in turn in the stored sequence. The start sequence input 36 when activated by a Start Sequence signal causes the address counter 30 to be reset to a base address value to access the start of the sequence in the memory 30, eg. at address zero. The counter can utilise a conventional integrated circuit device such as the 74AS867.

The providing section 20 is coupled to the output section 22 by a 16-bit data bus 38 from the output of the memory 24. The output section 20 includes an output latch 40 which is fed from 8 bits of the data bus 38. The latch 40 has a next run control input 42 which is coupled to the next run input 34 of the address counter 30. When activated by a Next-Run signal, the latch 40 is controlled to load in a value from the data bus 38, and provide it as an output 43 comprising 8 digital output lines. One of the output lines 43a is used as a Frame End line which is coupled to the Start Sequence input 36 of the counter 30 to provide the Start Sequence signal when the end of the stored sequence is reached.

The latch can utilise a conventional integrated circuit device such as the 74AS574.

The output section 22 also includes a counter timer 44 coupled to the remaining 8 bits of the data bus 38, for providing timing intervals determined by data on the data bus 38. The counter is a count down timer which repeatedly decrements a stored value until it reaches zero. The counter has an initial value input which is coupled to the data bus 38, a master clock input 50 which is fed by clock pulses from an external master clock source (not shown), and a next run control input 52 which is coupled to the next run inputs 34 and 42 of the counter 30 and latch 40, respectively. The counter timer also has an output 54 which is asserted when the counter reaches zero. The output 54 is coupled to the next run inputs 52, 34 and 42, to provide the Next Run control signals. The timer counter 44 may use an integrated circuit such as the 74F269.

Fig. 2 shows the form in which data is encoded in the memory 24. The memory is organised as 16-bit words. The first 8 bits 60 of each word store a run-length portion, or timing interval portion. The last 8 bits 62 store a bit pattern portion which represents the instaneous value of the logical states of the output lines 43. The last bit 62a of the bit pattern 62 is allocated for encoding a terminator flag or frame end bit which indicates that the end of the stored sequence has been reached. The bit position 62a is set to logical-zero in all of the words in the sequence except the last word in which the bit position 62a is set to a logical-one. The output line 43a can be used as a timing signal output line, but the timing signal generated on this line is preset as a pulse provided at the end of the sequence, ie. at the end of the period of the stored sequence.The other lines can be used to generate any set of timing signals.

The stored sequence is therefore a run-length encoded representation of the desired output signals. The bit patterns correspond to instaneous simultaneous values of the outputs, and the timing portion corresponds to the timing interval between consecutive bit patterns.

In use, the address counter 30 retrieves the stored data in the memory 24 in sequence and provides each data word on the data bus 38. The bit pattern portion 62 of the word is loaded into the output latch 40, and the timing portion 62 is loaded into the count down timer 44. The data in the output latch is provided as the output 43 until the count down timer 44 reaches zero, whereupon the Next Run Signal is toggled at the output 54. This causes the counter 30 to increment the address value to access the next word in the memory 24, and to load the corresponding bit pattern portion 60 and timing portion 62 of the next word into the latch 40, and counter timer 44, respectively. The new bit pattern is then provided as the output 43 for the timing interval determined by the asssociated timing portion.At the end of the timing portion, a next word is read from the memory 24, and the process is repeated.

When the last word in the sequence is read out from the memory, the bit pattern will contain the terminator flag, and the frame end output 43a from the latch 40 will be set to a logical-one. This value represents the Start Sequence signal which is fed to the counter 30. When the Next Run signal is asserted at the end of the timing interval for the last word in the sequence, the Start Sequence signal controls the counter 30 to be reset and loaded with the base address value corresponding to the intial word of the sequence in the memory 24. Thus the sequence of output signals will be repeated, providing a continuous periodic output.

In this embcx embodiment, the memory is organised as two pages, allowing two separate sets of timing signal waveforms to be stored and generated. The waveform set can be selected using the MapWr input 28.

The memory 24 can be a static RAM, or it can be pre-programmed ROM. Different sets of timing signals can also be selected by replacing one memory device with another. In other embodiments, the memory may be organised as a sequential output memory, i.e. as a shift register. The address counter would then be in the form of a shift pulse generator for controlling the shifting of data in the memory towards the output.

It will be appreciated that with the invention, the set of timing signals generated depends on the data encoded in the memory. The design of the hardware does not need to be changed in order to generate a new set of signals. To alter the timing signals, the memory can be re-programmed, or an alternative section of pre-programmed memory can be accessed.

Although in this embodiment, 8 bits are allocated for the bit pattern, and 8 bits for the timing information, the number of bits in each bit pattern can vary depending on the number of timing signals desired, and the number of bits for the timing information can vary depending on the resolution of timing interval desired.

One application for the timing generator is in the production and processing of either 625 line standard (e.g. PAL) or 525 line standard (e.g. NTSC) video or graphics signals. Two different sets of timing signals are commonly required, one for each video standard. The run-length encoded signals can be stored in the same memory, and selected by software control of the input MapWr 28 of the memory. Preferably, data rates of 13.5 ##Hz are used.

Claims (28)

CLAIMS:

1. A method for generating a plurality of periodic timing signals, wherein the signals are encoded as a sequence of bit patterns, each bit pattern having an associated timing parameter, the method comprising selecting each bit pattern in turn from the sequence, providing a plurality of output signals corresponding to the bit pattern for a time interval determined by the timing parameter associated with the bit pattern, and repeating the selection of bit patterns from the sequence when the end of the sequence is reached.

2. A method according claim 1, wherein the end of the sequence is identified by detecting a terminator flag encoded at the end of the sequence.

3. A method according to claim 2, wherein a logical bit is allocated with each bit pattern and associated timing parameter, for encoding the terminator flag.

4. A method according to claim 1, wherein the encoded sequence is stored in a digital memory.

5. A method according to claim 4, wherein an address counter is used to access bit patterns and associated timing parameters from the memory, the address counter being reset each time the end of the sequence is reached.

6. A method according to any preceding claim, wherein the time interval is determined by counting external clock pulses, the number of clock pulses counted being dependent on the value of the timing parameter.

7. Apparatus for generating a plurality of periodic timing signals, comprising means for providing a sequence of bit patterns with associated timing parameters, means for selecting each bit pattern of the sequence in turn, means for outputting a plurality of digital signals corresponding to each selected bit pattern for a time interval determined by the associated timing parameter, and means for causing the selecting means to repeat selection of bit patterns from the sequence each time the end of the sequence is reached.

8. Apparatus according to claim 7, wherein the providing means comprises a digital memory containing the sequence of bit patterns and associated timing parameters, and the selecting means comprises an address counter coupled to the memory for sequentially accessing the sequence.

9. Apparatus according to claim 8, wherein the means for causing the sequence to be repeated comprises means for detecting the end of the sequence as it is accessed from the memory, and means coupled to the address counter for resetting the address counter to access the beginning of the sequence.

10. Apparatus according to claim 9, wherein the detecting means comprises means for detecting a terminator flag encoded at the end of the the sequence.

11. Apparatus according to claim 10, wherein the detecting means comprises means for checking a logical bit position encoded with each bit pattern and associated timing parameter, which logical bit position is allocated for encoding the terminator flag.

12. Apparatus according to claim 7, wherein the output means includes an output latch into which the bit pattern is loaded.

13. Apparatus according to claim 7, wherein the output means includes a clock pulse counter timer for determining the timing interval from the timing parameter

14. Apparatus according to claim 13, wherein the counter timer is a count down timer into which the timing parameter is loaded, the value in the counter timer being decremented by clock pulses until the value is zero.

15. A method of encoding a plurality of periodic timing signals, comprising encoding the signals as a sequence of bit patterns and associated timing parameters, wherein the bit patterns correspond to simultaneous logical values of the plurality of signals and the timing parameters correspond to time intervals between consecutive bit patterns in the sequence.

16. A method according to claim 15, wherein a terminator flag is encoded at the end of the sequence.

17. A method according to claim 16, wherein a logical bit position is allocated with each bit pattern and associated timing parameter for encoding the terminator flag.

18. A method according to claim 15, wherein the encoded sequence is stored in a digital memory.

19. A method according to claim 18, wherein the bit patterns and associated timing parameters are stored together in locations of the memory, the sequence forming a contiguous block of data.

20. A preprogrammed memory device for use in the generation of a plurality of periodic timing signals, the memory containing at least one sequence of bit patterns and associated timing parameters, which sequence is an encoded representation of the timing signals to be generated, the bit patterns corresponding to simultaneous logical values of the plurality of signals and the timing parameters corresponding to time intervals between consecutive bit patterns.

21. A memory according to claim 20, wherein the memory is a read only memory (row).

22. A memory according to claim 20, wherein the sequence includes a terminator flag indicating the end of the sequence.

23. A memory according to claim 22, wherein a logical bit position is allocated with each bit pattern and associated timing parameter for encoding the terminator flag.

24. A memory according to claim 20, wherein the bit patterns and associated timing parameters are stored together in locations of the memory, the sequence forming a contiguous block of data.

25. A plurality of simultaneous timing signals, generated according to the method of claim 1.

26. Apparatus substantially as hereinbefore described with reference to Fig. 1 of the acooanyinmg drawings.

27. A method of generating a plurality of timing signals substantially as hereinbefore described with reference to the accompanying drawings.

28. A method of encoding a plurality of timing signals substantially as herinbefore described with reference to Fig.2 of the accompanying drawings.