GB2212358A

GB2212358A - Method and apparatus for deriving synchronising signals

Info

Publication number: GB2212358A
Application number: GB8825861A
Authority: GB
Inventors: Gerhard Wischermann
Original assignee: BTS Broadcast Television Systems GmbH
Current assignee: Philips GmbH
Priority date: 1987-11-06
Filing date: 1988-11-04
Publication date: 1989-07-19
Anticipated expiration: 2008-11-04
Also published as: FR2623039B3; DE3737730C2; FR2623039A1; GB8825861D0; DE3737730A1; GB2212358B

Description

k q 1 2212358 METHOD AND ARRANGEMENT FOR DERIVING SYNCHRONISING SIGNALS

This invention relates to a method and an arrangement for deriving synchronising signals.

It.is known in connection with the transmission of a digital video signal to transmit the synchronisation information within the horizontal frequency blanking intervals in the form of a given sequence of data words, known as the time reference signal. According to CCIR recommendations 601 and 656, a time reference signal com- prises three so-called preamble words with a constant content, namely 255, 0 and 0, and a fourth data word with a variable content. The latter is referred to hereinafter as the time reference word T and has the following composition: (1,F,V,H,P3,P2,Pl,PO). F is a field identification bit and is set to 1 during alternate fields and to 0 during the intermediate fields. Bit V is set to 1 at the start of each field, whilst bit H is set to 1 in the time reference word transmitted at the beginning of a horizontal frequency blanking interval and to 0 in the time reference word transmitted at the end of the horizontal frequency blanking interval. The positions (bits) P3 to P1 represent check bits which, according to a Hamming code, are derived from F, V and H, whilst PO is a parity bit.

2.5 On the reception side this coding of the synchronisation information permits a correction of 1 bit errors. It is also possible to detect, but not correct, 2 bit errors. Such bit errors can occur. for example, in the case of 1 long transmission distances as a result of attenuation losses or through the drop-out of one or two bits, or through reciprocal short circuiting in individual apparatuses.

The interfering effect of occasional errors in data words of the original digital video signal which represent the image content is limited. However, errors during the transmission of the time reference signal can lead to a failure of synchronisation, which, as is known, can have a very considerable interference effect.

The object of the present invention is therefore to prevent such a failure of synchronisation, even in the case of occasionally occurring 2 bit errors in the time reference word.

Accordingly, the present invention provides a method for deriving synchronising signals from a digital video signal containing time reference signals each comprising several data words with a predetermined content, wherein successive data words of the video signal are checked for conformance with successive data words of the time reference signals except that in the event of non-conformance being found at any stage of the checking, the checking starts again with respect to the first data word of the time reference signals, and wherein when all the data words of a time reference signal have been detected at least one detection signal is produced which is used to re-set a counter circuit arranged to count clock signals coupled to the video signals. the counter circuit generating at least one sync signal at a certain count value and being selfresetting in the absence of a detection signal being generated with respect to a subsequent erroneous time reference signal.

The method according to the present invention has the advantage that the synchronising signals are derived from the digital video signal with high reliability despite errors of up to 2 bits within the time reference signal. Even if time reference words are only occasionally transmitted with no or a 1 bit error, synchronisation is ensured.

Although the method according to the invention can be particularly advantageously used for deriving synchronising signals from the time reference signal according to the aforementioned CCIR recommendations, the invention is also suitable for other time reference signals.

An arrangement for performing the invention, which uses a state-mavhine for deriving preliminary sync signals, - is characterized by limited technical expenditure and makes full use of the advantages of the inventive method.

An embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which:

Fig. 1 is a simplified block circuit diagram of an arrangement for performing the method according to the invention; Fig. 2 is a block circuit diagram of a statemachine; Fig. 3 is a state diagram of the state-machine of Fig.2; Fig. 4 are timing diagrams of the data occurring in the state-machine of Fig. 2; Fig. 5 is a block circuit diagram of a digital flywheel circuit. and Figs. 6 and 7 are timing diagrams of signals occurring in the circuit arrangement of Fig. 5.

Referring to the drawings, in Fig. 1 video data is supplied at an input 1 to a state-machine 2 as a preferably 8 bit wide digital video signal. The state-machine 2 and a counter circuit 3, which contains counters 4 and 5 for deriving horizontal and vertical frequency sync pulses H and V, as well as a field identification signal

F, are timed with a 27 MHz system clock CS supplied at 6 and which is transmitted in parallel with the digital video signal. The state-machine 2 will be described in greater detail with reference to Figs. 2 and 4, and the counter circuit 3 will be described in greater detail with reference to Figs. 5 to 7. The counter circuit 3 is a digital flywheel circuit supplying the sync pulses H, V, and F at outputs 7, 8 and 9 respectively and which are obtained by frequency division of the system clock. As the system clock is derived from and hence is coupled with-the video data (digital video signal at input 1), synchronisation of the counter circuit 3 is only necessary j, when switching on or after a fault has occurred. No faults occur if as a result of errors in the time intervals of the video data incorporating the synchronisation information, the state-machine 2 temporarily supplies no 5 sync pulses H3 or F3 to the counter circuit 3.

The state-machine shown in Fig. 2 comprises a read-only memory 11 and a Dregister 12, which is timed by the system clock CS. Two outputs of the read-only memory 11 are returned to inputs thereof across the D-register 12. The combination of values of these signals S1 and S2 stored in the D-register 12 characterize the particular state of the state-machine. The video data, comprising 8-bit words supplied in parallel to the 8 inputs of the read-only memory 11, contains a time reference signal at the start and finish of each horizontal frequency blanking interval. As a function of the values of the video data words, passage through the state diagram of Fig. 3 occurs. Four states, ZO, Z1, Z2 and Z3 are pos- sible corresponding to respective combinations of values of the signals S1 and S2. State ZO is only left if the current data word of the video data supplied at input 1 has the value 255. Otherwise, across the Dregister 12, the values for S1 and S2 characterizing this state ZO are again supplied to the corresponding inputs of the read-only memory 11 so that, as indicated in Fig. 2, the state-machine is in a wait loop.

However, upon detection of a data word with the value 255 the state-machine is brought into state Z1, from which it.passes into state Z2 if the next following data 1 6- word has the value 0, but is otherwise returned to the state ZO. A similar check also takes place in state Z2 to establish whether the following data word also has the value 0. If this is the case, then state Z3 is entered, which means that the first three data words of the time reference signal have been identified. Otherwise, the state machine reverts to ZO.

From state Z3 the state machine always passes to state ZO. However, depending upon whether the time reference word T has been correctly identified, signals F1 and H1 are read out of the read-only memory 11 and written into the D-register 12 under the control of a loading signal LD1. If the time reference word T is not identified, then no signal LD1 is generated.

These processes are shown in Fig. 3, the system clock CS being represented in line (a). Line (b) shows the video data for the four data words of the time reference signal.

Lines (c) and (d) show respectively the state and the next state of the state-machine, whilst line (e) shows the loading signal LD1 for the Dregister 12 which only occurs if the time reference word T is correct or comprises only one erroneous bit, which in known manner is corrected by appropriate programming of the read-only memory 11. Signals F1, H1 and LD1 are fed out of the D-register 12 delayed by one clock cycle. The delayed signals F2, H2 are fed to the inputs of a further Dregister 13, whilst the delayed signal LD2 controls a loading input of the D-register 13 in such a way that the signals F2 and H2 are only transferred into the D- 7 1 -1 register 13 if an LD2 signal is present. The outputs of the D-register 13 form the outputs 14, 15 of the statemachine, from which it is possible to take signals F3 and H3 for supply to the digital flywheel circuit arrange5 ment of Fig. 5.

To the digital flywheel circuit of Fig. 5 the system clock is supplied at 21, the signals H3 at 22, and the signals F3 at 23. The system clock CS drives a first coun ter 24 which, after counting 1728 pulses of the system clock CS, supplies a pulse of a further clock signal Cl.

Eleven outputs of counter 24 are connected to respective inputs of a logic circuit 25, at whose output 26 the sync signalHis generated. Logic circuit 25 is constructed to be responsive to the counter 24 in such a way that for a given count range of the counter 24 the signal H assumes a binary value different from that for the remeining range.

Via an OR circuit 27 the pulse Cl resets the counter 24 on reaching the counter reading of 1728. A pulse H4 is applied to a further input of the OR circuit 27, the pulse H4 being derived by a pulse shaper 28 from the trailing edge of the pulse H3 supplied at 22.

If an error-free or correctable time reference signal is not supplied to the input 1 (Fig.1), then the counter 24 is reset by the pulse Cl. Otherwise, the pulse H4 resets the counter 24, ideally simultaneously with the pulse Cl which is the case with normal equilibrium 30 operation.

Signal Cl is supplied to a second counter 29 which, after counting 625 pulses of the signal Cl, supplies a pulse of a further clock signal C2. By means of a logic circuit 30 responsive to given count ranges of the counter 29, sync signals F and V are generated at outputs 31 and 32. In much the same way as for counter 24, counter 29 is reset by the pulse C2 supplied across an OR circuit 33, and/or by a pulse P4 supplied to a further input of the OR circuit 33 and obtained by means of a pulse shaper 34 from the pulse F3 supplied at 23.

Thus, even though the pulses H4 and F4 may be missing from time to time due to intermittent incorrectable time reference signals, the pulses Cl and C2 maintain the fly- wheel circuit in sync with the video data until new pulses H4 and F4 are produced.

Advantageously, each of the logic circuits 25 and 30 is constituted by a programmable read-only memory containing a look-up table.

The generation of the horizontal frequency sync signal H will now be explained with reference to Fig. 6. The. system clock CS has a frequency of 27 MHz. As described above, at time tO the position of the D-register 13 (Fig.2) used for storing the signal H3 is set to the value 1 because the D-register 13 is supplied with a loading pulse LD2 and a signal H2 with the binary level 1. This is because the corresponding bit of the time reference word T of the time reference signal transmitted at the start of the horizontal frequency blanking pulse was a 1. At the i 11 end of the blanking interval a further time reference signal is transmitted, whose H bit is 0, so that the D-register 13 is set to 0 (time tl).

The trailing edge of the signal H3 drives the pulse shaper 28 and supplies the signal H4. which has a duration of one clock cycle CS. This resets the counter 24 which, after 1728 clock cycles, supplies a signal Cl (Fig. 6 shows that pulse of the signal Cl which resul- ted from the preceding counting process). By means of one or both of the pulses H4 and Cl, the resetting pulse Ll occurs at the output of the OR circuit 27, and the counter 24 then starts to count up from the beginning again (zero). As a result of a suitable connection of the outputs of the counter circuit 24 with the logic circuit 25 the pulse H shown in Fig. 6 is produced, and also if H4 pulses drop-out due to two or more erroneous bits in the time reference word.

Fig. 7 shows the generation of the vertical frequency sync signal V and the field identification signal F. By appropriately setting the particular bit in the time reference word T and the transfer of this information into the D-register 13, the signal F3 is formed which during each first field assumes the binary value 0 and during each second field the binary value 1. From the trailing edge of the signal F3 the pulse F4 is derived and this and/or a pulse of the signal C2 is used for resetting the counter 29 (Fig. 5). If at least one of the pulses F4 and C2 occurs, the resetting pulse L2 is produced. As mentioned before, each pulse of the signal C2 is produced when the counter 29 reaches the counter reading of 625. The two signals F and V are obtained by appropriate logic connections from the 10 bit wide output signal of counter 29 to the logic circuit 30.

1 J i

Claims

CLAIMS.

1. A method for deriving synchronising signals from a digital video signal containing time reference signals each comprising several data words with a predetermined content. wherein successive data words of the video signal are checked for conformance with successive data words of the time reference signals except that in the event of non-conformance being found at any stage of the checking the checking starts again with respect to the first data word of the time reference signals, and where- in when all the data words of a time reference signal have been detected at least one detection signal is produced which is used to re-set a counter circuit arranged to count clock signals coupled to the video signals, the counter circuit generating at least one sync signal at a certain count value and being selfresetting in the absence of a detection signal being generated with respect to a subsequent erroneous time reference signal.

2. A method according to claim 1, wherein the time reference signals each comprises three data words with a constant content and one further data word which contains line and field information, wherein as a function of the content of the further data word detection signals in the form of preliminary line frequency and preliminary field frequency sync signals are produced, and wherein by counting the clock signals horizontal frequency sync signals are produced and by counting a sub-set:bf the clock signals vertical frequency sync signals are produced, counting of the clock signals being reset by the preliminary horizontal frequency sync signals and counting of the sub-set of the clock signals being re-set by the preliminary field frequency sync signals.

3. A method according to claim 2, wherein the line and field information in the further data word is coded in error-co rrecting manner, and wherein in the case of a further data word which is error-free or has a correctable error preliminary sync signals are produced whereas in the case of an uncorrectable further data word no preliminary sync signal is produced.

4. An arrangement for deriving sync signals from a digital video signal containing time reference signals each comprising several data words with a predeterminedcontent, wherein the digital video signal is-supplied to a state-machine, the outputs of the state-machine are connected to inputs of a digital flywheel circuit from whose outputs are taken the sync signals, and a clock signal derived from the digital video signal is supplied to the state-machine and to the digital fly20 wheel circuit.

5. An arrangement according to claim 4, wherein the state-machine comprises a read-only memory with a multi-position data putput, and wherein a number of positions of the data output are connedted across a Dregister to the same number of positions of the memory address input, the number of positions being chosen in such a way that a number of states of the state-machine can be defined which corresponds to the number of data 30 words of the time reference signals.

11

6. An arrangement according to claim 51 wherein the digital video signal contains 8-bit parallel data words and the time reference signals comprise three data words with a constant content and a further data word with a varying content, and wherein the address input of the read- only memory has ten positions and the data output five positions, all the positions of the data output being connected to the inputs of said Dregister, two outputs of the D-register being connected to two positions of the address input of the read-only memory, two further outputs being.connected to inputs of a further D-register, and the fifth output being connected to a loading input of the further D- register.

7. An arrangement according to any one of claims 4 to 6,. wherein the digital flywheel circuit comprises first aiid second counters, the input of the first counter is supplied with the clock signal, a carry output of the first counter is connected across a first OR circuit to a resetting input of the first counter and with a counting input of the second counter, a carry output of the second counter is connected across a further OR circuit to a resetting input..of the second counter, a first output of the state-machine is supplied across the first OR circuit to the resetting input of the first counter, a second output of the state-machine is supplied across the further OR circuit to the resetting input of the second counter. outputs of the first and second counters are connected to first and second logic circuits respectively, and the first logic circuit has an output for the horizontal frequency sync signals and the-second logic circuit has outputs for vertical frequency sync signals and field identification signals.

8. A method according to claim 1, substantially as described with reference to the accompanying drawings.

9. An arrangement for performing the method of claim 1, substantially as described with reference to the 10 accompanying drawings Published 1989 at The Patent Office, State House, 66.071 High Holborn. London WC1R 4TP. Further copies maybe obtained from The Patent Office. Sales Branch, St MarY CMY, OrPington. Kent BR5 31M. Printed by MUltiPlex techniques ltd, St MarY CraY, Kent. Con. 1167 A 11 -t-