GB2306263A - Generation of composite television synchronization signal - Google Patents

Abstract

An arrangement for generating a composite television synchronization signal CS comprises a clock pulse counter 2 for deriving line pulses from a clock pulse signal 1 and a line pulse counter 4 for generating successive line numbers n. In order to decode said counters to produce the required synchronization pulses, the arrangement comprises a memory 5 in which, for each line n, a multi-bit sync code is stored. Said sync codes are indicative for the synchronization pulses to be generated during said line. Preferably, the memory 5 is programmable. One of the sync codes is used to produce a reset signal RS for the line counter 4 so that the same arrangement is suitable for different television systems.

Description

Generation of a composite television synchronization signal.

FIELD OF THE INVENTION The invention relates to an arrangement and method for generating a composite television synchronization signal. The invention also relates to a graphic image generator comprising such an arrangement.

BACKGROUND OF THE INVENTION Fig. 1 shows the well-known composite television synchronization signal for 625 line, 50 Hz television systems. Arrangements for generating this synchronization signal generally comprise means for receiving a clock pulse, a clock pulse counter for producing line pulses, and a line pulse counter. The particular sequence of pulses shown in Fig. 1 is obtained by decoding said counters in an appropriate manner. Conventional arrangements comprise hardwired decoding logic circuitry for that purpose. Said circuitry occupies a considerable amount of chip area of an integrated circuit. Further, the known arrangements require additional circuitry if they are to suit other (e.g. 525 line, 60 Hz) television systems as well.

OBJECT AND SUMMARY OF THE INVENTION It is an object of the invention to provide an improved arrangement for generating a composite television synchronization signal.

According to the invention, the arrangement is characterized in that the decoding means comprise a memory addressed by the line pulse counter, and means for generating, for each line, synchronization pulses being defined by a sync code stored in said memory for said line. The various synchronization pulses to be produced are now defined by the contents of the memory. Preferably, the memory is programmable so that a plurality of synchronization modes (such as interlaced or non-interlaced) are easily selectable by reprogramming the memory.

In an embodiment, the arrangement comprises a detection circuit adapted to detect a predetermined sync code stored in said memory, and to apply a reset signal to the line counter in response to said detection. Herewith, the number of TV lines can easily be adapted to PAL or NTSC.

The invention is particularly useful in graphic image generators. Graphic image generators already comprise a display memory for storing the graphic image to be produced as well as clock pulse counters and line pulse counters for accessing said display memory. The composite television synchronization signal can be obtained almost free by using only a small section of said display memory for storing the sync codes.

Particularly attractive is an embodiment of the arrangement wherein the memory stores a sync code for each of two fields. The embodiment comprises a divideby-2 circuit receiving the reset signal to produce a field identification signal for identifying one of said fields, and means for applying a sync code to the generating means in response to said field identification signal. With this embodiment, an interlaced graphic image comprising twO identical fields can effectively be displayed.

BRIEF DESCRIPTION OF THE FIGURES Fig. 1, already discussed, shows the waveform of a composite synchronization signal for 625 lines, 50 Hz television systems.

Fig.2 shows a schematic diagram of an arrangement for generating a composite television synchronization signal according to the invention.

Fig.3 shows some waveforms to illustrate the operation of a decoder shown in Fig.2.

Fig.4 shows a schematic diagram of a graphic image generator according to the invention.

Fig.5 shows the waveform of a non-interlaced composite synchronization signal.

Fig.6 shows a further embodiment of the arrangement according to the Invention.

Fig.7 shows a further embodiment of a graphic image generator according to the invention.

Fig.8 shows a television receiver according to the invention.

DESCRIPTION OF EMBODIMENTS Fig.2 shows a schematic diagram of an arrangement for generating a composite television synchronization signal according to the invention. The arrangement receives a clock pulse signal F12 having a frequency of 12 MHz via an input 1. The clock signal F12 is applied to a divide-by-768 clock pulse counter 2 which generates the television line frequency of 15625 Hz. The counter states are decoded by a decoder 3 which is arranged to produce a timing signal H at the line frequency, as well as normal sync pulses NP (56 clock periods), equalizing sync pulses EP (28 clock periods), and broad sync pulses BP (328 clock periods). A suitable embodiment of decoder 3 can easily be derived from the waveforms shown in Fig.3.

The sync pulses NP at the line frequency are applied to a line counter 4 which, in response thereto, generates successive line numbers n for addressing a memory 5. For each line n, said memory stores a 2-bit sync code Sl and a 2-bit sync code S2. Both sync codes are applied to a selector 6, which selects one of them in response to the timing signal H. During the first half of a line (H =0), the sync code S1 is selected. During the second half of a line (H = 1), the sync code S2 is selected.

The selected sync code (S1 or S2) constitutes a 2-bit selection signal S for a 4-input multiplexer 7. The inputs thereof receive the sync pulses BP, EP, NP, and a fixed level 0, respectively. The multiplexer 7 selects the broad sync pulse BP if S = 11, the equalizing pulse EP if S=10, the normal pulse NP if S=01, and no pulse (the fixed level 0) if S=00. The output of the multiplexer constitutes the composite synchronization signal CS which is, apart from possible polarity inversion, applied to an output terminal 8.

Each pair of 2-bit sync codes S1,S2 stored in memory 5 thus determines whether or not a sync pulse is generated in the first and second half of a television line, and the width of the pulse. For 625 lines, 50 Hz systems as shown in Fig.1, it will be appreciated that the locations of memory 5 addressed by line numbers n=6..310 and n=319..622 will store the sync code pair [01,00] so as to produce a normal sync pulse in the first half of a line and no pulse at all in the second half. For n=1,2 and n=314,315 the sync code pair [11,11] is stored so as to produce two broad sync pulses.

For n=4,5, n=311,312, n=316,317, and n=624,625 the sync code pair [10,10] is stored so as to produce two equalizing pulses. Finally, for n=3 the stored sync code pair is [11,10], and for n=313 the stored sync code pair is [10,11]. If desired, different composite synchronization signal waveforms can be generated by reprogramming the memory 5. Some examples thereof will be described later.

Above described is the basic principle of the arrangement. In practice, some additional circuit elements are necessary in order to cope with the access time ("latency") of memory 5. To cover the gap between issuing a line pulse NP to line counter 4 and the arrival, up to 1 ys later, of the stored sync code pair S1 or S2, the shortest pulse EP is forced onto the composite synchronization signal CS at the start of each line (H =0). This is performed by an AND-gate 9 and a NOR-gate 10.

In the embodiment described above, the line counter 4 is assumed to be a divide-by-625 counter which cycles through line numbers n=l to n=625. In order to have also the number of lines determined by a code stored in memory 5, the arrangement further comprises a decoding circuit 11 which receives the sync code pair S and the timing signal H. The decoding circuit detects the occurrence of sync code S1 =00 (no sync pulse) during the first half of a line (H =0). For sync pulse generation, this is an illegal code. Upon detection of this code, the decoding circuit 11 applies a reset signal RS to the line counter 4 so as to reset this counter (e.g. to ni) and to cause memory 5 to produce a legal sync code as yet.The arrangement is thus adapted to produce any number of lines by storing the sync code Ski =00 at an appropriate memory address (e.g. at n=626 for PAL systems and n=526 for NTSC systems).

Fig.4 shows a graphic image generator comprising the arrangement shown in Fig.2. In Fig.4, the same numerals are used for the same circuit elements as shown in Fig.2. The graphic image generator comprises a random-access-memory (RAM) 20 which is, for example, 4-bit wide. The RAM is connected, via a data and address bus 21, with a microprocessor (not shown) so as to be programmable under control of a program stored in said pP. For display purposes, the RAM is addressed by line number n (already discussed) from line counter 4, and a pixel number m from clock pulse counter 2. In a display section 201 of the RAM, 480 4-bit pixels are stored for display during the active part of each TV-line. They are applied to a colour-look-up-table 22 so as to be converted into full-colour display signals R, G, and B. This method of generating a graphic image is well-known in the art.

RAM 20 further comprises a sync control section 202. This section corresponds to memory 5 of Fig.2 and holds, for each line n, the sync code pairs [Sl,S2] defining the synchronization pulses to be generated. The sync code pairs [S1,S2] are read from memory at the beginning of each line, held in a register (not shown), and applied to selector 6.

The embodiment shown in Fig.4 is particularly attractive because image generators already comprise the RAM 20 for storing the graphic image to be produced as well as the clock pulse counter 2 and line pulse counter 4 for accessing said display memory. The composite television synchronization signal can thus almost free be obtained by adding only a small section 202 to RAM 20 for storing the sync codes.

The composite television synchronization waveform shown in Fig. 1 causes a television receiver to display an interlaced image, because the vertical sync pulse (V in Fig. 1) coincides with a horizontal sync pulses in one field and is positioned in the middle of a line in the other field. The information displayed in both fields can be different or the same. The first option is further referred to as "interlaced rounded" display mode whereas the second option is further referred to as "interlaced nonrounded" display mode. It can easily be understood that the "interlaced non-rounded" display mode requires the same display information (i.e. pixels) to be stored twice, namely, in pairs of lines of display memory 20 (Fig.4).

The arrangement according to the invention can also easily be programmed to operate in a "non-interlaced non-rounded" display mode. To that end, the arrangement is programmed to generate the composite synchronization signal shown in Fig.5. This signal now comprises a single vertical sync pulse V only. The "noninterlaced non-rounded" display mode does not require the pixels to be stored twice and thus offers a significant advantage.With reference to Fig.5, it will be appreciated that in this mode the locations of memory section 202 addressed by line numbers n=1,2 will store the sync code pair [11,11] so as to produce two broad sync pulses, the location at n=3 will store the sync code pair [11,10] so as to produce a broad pulse and an equalizing pulse, the locations at n=4,5 and n=311,312 will store the sync code pair [10.10] so as to produce two equalizing pulses, the locations at n=6..309 will store the syllc code pair [01,00] so as to produce a normal sync pulse, and the location at n=310 will store the sync code pair [01,10] so as to produce a normal and an equalizing pulse.

In the location at n=313, the sync code pair [00,xx] is programmed so as to produce the reset pulse RS for resetting the line counter as yet to n = 1. Thus, a 312-line noninterlaced image is obtained on PAL television receivers. In a similar way, a 262-line non-interlaced image can be displayed on NTSC television receivers.

Fig.6 shows a further embodiment of an arrangement according to the invention. Besides the display modes already described, this embodiment offers another "interlaced non-rounded" display mode without requiring the pixel information to be stored twice in display memory.

In Fig.6, the same numerals are used for the same circuit elements as shown in Fig.2. The arrangement now comprises a flipflop 12 which divides the reset signal RS by 2 so as to identify an odd and an even television field. The output signal is denoted O/E. The memory 5 now comprises four sync codes per TV line. The sync code pair [S1,S2] defines the sync pulses to be produced in the odd field, in a manner as described before. A further sync code pair [S3,S4] defines the sync pulses to be produced in the even field, in a similar manner. A group of four sync codes [S1,S2,S3,S4] will hereinafter be referred to as "sync code group". The arrangement further comprises a selector 13 to select the appropriate sync code pair in response to the O/E signal, and a selector 14 to select the sync code for the first or second half of a line.

For displaying an "interlaced non-rounded" graphic image on a 625-lines PAL television receiver, the memory 5 (or, with reference to Fig.4, display memory section 202) is programmed according to Table I.

n S1 S2 S3 S4 odd even 1 11 11 11 11 BP BP BP BP 2 11 11 11 11 BP BP BP BP 3 11 10 10 10 BP EP EP EP 4 10 10 10 10 EP EP EP EP 5 10 10 10 00 EP EP EP 6-309 01 00 01 00 NP - NP 310 01 00 01 10 NP - NP EP 311 10 10 10 10 EP EP EP EP 312 10 10 10 10 EP EP EP EP 313 10 11 00 xx EP BP reset 314 00 xx reset

Table I In Table I, the first column indicates the line numbers n as applied to memory 5 by line counter 4. The second column shows the sync code groups [S1,S2,S3,S4] stored at said memory locations. The third column indicates which type of sync pulses (broad pulses BP, equalizing pulses EP, normal pulses NP or no pulses) are produced by the arrangement during the first and second half, respectively, of the lines of the odd field. The synchronization signal thus generated corresponds with lines 1-312 of Fig.l. The fourth column indicates which type of sync pulses are produced during the first and second half, respectively, of the lines of the even field. The synchronization signal now generated corresponds with lines 314-625 of Fig. 1.

Special attention is drawn to the generation of reset signal RS. If the line number n arrives at n=314, odd field, the sync code pair [S1,S2]=[00,xx] forces the counter 4 to be reset to n=l, and the flipflop 12 to be toggled to the even state. As a result, two broad pulses BP are produced in accordance with n=l, even column. The sync pattern thus generated corresponds to line 314 in Fig.l. If the line number n then arrives at n=313, even field, the sync code pair [S3,S4]=[00,xx] forces the counter 4 to be reset to n=l, and the flipflop 12 to be toggled to the odd state. Now, two broad pulses BP are produced in accordance with n=l, odd column. The sync pattern thus generated now corresponds to line I in Fig. 1. The image generator thus produces a "non-rounded" image because the pixel information in line n of memory is read during line n and n+313 of the synchronization signal, whereas the synchronization signal fed to the television receiver is "interlaced".

Obviously, the arrangement shown in Fig.6 can be incorporated in a graphic image generator, taking advantage of the fact that the memory, clock pulse counter and line pulse counter are already available in said graphic image generator.

Fig.7 shows such a graphic image generator. A detailed description hereof is not necessary in view of the explanation of the image generator shown in Fig.4.

Fig.8 shows a television receiver comprising a graphic image generator.

The television receiver comprises well-known circuit elements such as an antenna 101, a tuner and demodulator 102, a video processing circuit 103, a sync detector 104, a deflection stage 105, and a display device 106 having deflection coils 107. A graphic image generator 108 produces, as explained above, a display signal RGB and a corresponding composite synchronization signal CS. The display signal RGB is applied to video processing circuit 103. A switching circuit 109 applies either the received synchronization signal from sync detector 104 or the synchronization signal CS from image generator 108 to the deflection circuit 105. In a "TV mode" (switch in the position shown), the deflection stage 105 receives the synchronization signal associated with the received video signal.In a "stand-alone mode", the deflection stage receives the composite synchronization signal CS from image generator 108.

In summary, an arrangement and method for generating a composite television synchronization signal (CS) is described. The arrangement comprises a clock pulse counter (2) for deriving line pulses from a clock pulse signal (1) and a line pulse counter (4) for generating successive line numbers (n). In order to decode said counters to produce the required synchronization pulses, the arrangement comprises a memory (5) in which, for each line n, a multi-bit sync code is stored. Said sync codes are indicative for the synchronization pulses to be generated during said line. Preferably, the memory (5) is programmable. One of the sync codes is used to produce a reset signal (RS) for the line counter (4) so that the same arrangement is suitable for different television systems.

The invention renders it possible, inrer alia, to generate stable teletext or On-Screen-Display images in television receivers and videorecorders when no television signal is being received. The invention can further be used in game equipment, personal computers, CDi players. and CDVideo players.

Claims (13)

Claims

1. An arrangement for generating a composite television synchronization signal, comprising means for receiving clock pulses, a clock pulse counter for producing line pulses, a line pulse counter, and decoding means for decoding said counters so as to produce the composite synchronization signal, characterized in that the decoding means comprise a memory addressed by the line pulse counter, and means for generating, for each line, synchronization pulses being defined by a sync code stored in said memory for said line.

2. Arrangement according to claim 1, wherein the memory is programmable.

3. Arrangement according to claim 1 or 2, further comprising a detection circuit adapted to detect a predetermined sync code stored in said memory, and to apply a reset signal to the line counter in response to said detection.

4. Arrangement according to claim 3, wherein the memory stores a sync code for each of two fields, further comprising a divide-by-2 circuit receiving said reset signal to produce a field identification signal for identifying one of said fields, and further comprising means for applying a sync code to the generating means in response to said field identification signal.

5. A graphic image generator comprising a display memory for storing information to be displayed, and a clock pulse counter and a line pulse counter for addressing said memory to read the information to be displayed, characterized in that said display memory comprises memory locations for storing, for each line, a sync code defining synchronization signals to be generated during said line, and means for generating said synchronization pulses defined by said sync code.

6. Image generator according to claim 5, wherein the memory is programmable.

7. Image generator according to claim 5 or 6, further comprising a detection circuit adapted to detect a predetermined sync code stored in said memory, and to apply a reset signal to the line counter In response to said detection.

8. Image generator according to claim 7, wherein the display memory stores a sync code for each of two fields, further comprising a divide-by-2 circuit receiving said reset signal to produce a field identification signal for identifying one of said fields, and further comprising means for applying a sync code to the generating means in response to said field identification signal.

9. A method of generating a composite television synchronization signal, comprising the step of counting clock pulses to produce line pulses, counting line pulses to produce line numbers, and decoding said counts so as to produce the composite synchronization signal, characterized in that the step of decoding comprises the step of reading for each line number a sync code from a memory, and generating synchronization pulses defined by said stored sync codes.

10. Method according to claim 9, further comprising the step of detecting a predetermined sync code stored in said memory, and resetting the line count in response to said detection.

11. Method according to claim 10, wherein the memory stores a sync code for each of two fields, further comprising the step of dividing-by-2 said reset signal to produce a field identification signal for identifying one of said fields, and generating the synchronization pulses in response to said field identification signal.

12. A receiver of television signals comprising an arrangement for generating a composite television synchronization signal as claimed in any of claims 1-4.

13. A receiver of television signals comprising a graphic image generator as claimed in any of claims 5-8.