EP0119260A1 - Cmos integrated circuit with guard bands for latch-up protection - Google Patents

Cmos integrated circuit with guard bands for latch-up protection

Info

Publication number
EP0119260A1
EP0119260A1 EP83903252A EP83903252A EP0119260A1 EP 0119260 A1 EP0119260 A1 EP 0119260A1 EP 83903252 A EP83903252 A EP 83903252A EP 83903252 A EP83903252 A EP 83903252A EP 0119260 A1 EP0119260 A1 EP 0119260A1
Authority
EP
European Patent Office
Prior art keywords
plus
guard bands
cmos integrated
integrated circuit
wells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83903252A
Other languages
German (de)
French (fr)
Other versions
EP0119260A4 (en
Inventor
Paul Denham
Patrick Charles Allen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SEMI PROCESSES Inc
Original Assignee
SEMI PROCESSES Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SEMI PROCESSES Inc filed Critical SEMI PROCESSES Inc
Publication of EP0119260A1 publication Critical patent/EP0119260A1/en
Publication of EP0119260A4 publication Critical patent/EP0119260A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

Definitions

  • Latch-up is a potentially serious problem in the operation of CMOS integrated circuits. Latch-up is caused by the formation of parasitic bipolar transistors which are byproducts of both p-channel and n-channel devices.
  • the susceptibility of a CMOS integrated circuit chip to latch-up is a function of the starting material, the processing procedure, and the circuit and chip design techniques.
  • adjacent pMOS and nMOS devices form parasitic npn and pnp devices. Together this constitutes a four layer pnpn path which results in an operation like a silicon controlled rectifier (SCR).
  • SCR silicon controlled rectifier
  • Injected minority carrier current may accidently trigger the structure. After triggering, the structure can be turned off only by turning off the power. This triggering can occur when the injected current causes a voltage transient in the circuit that is either above the circuit power supply or below ground.
  • guard bands or rings are p-plus diffusions in the substrate surrounding pMOS transistors, and n-plus diffusion in the p-well surrounding nMOS transistors.
  • the p-plus guard band is tied to ground, and the n-plus is tied to the supply voltage, Vdd.
  • the guard bands reduce the parasitic bipolar transistor beta product by collecting injected minority carriers, and by increasing the distance between adjacent nMOS and pMOS devices.
  • guard bands In order to collect a significant fraction of the injected minority carriers, the width of these guard bands typically must be in the same order of magnitude as the p-well diffusion depth of the nMOS devices. Typically this is about 8 microns.
  • the spacing between the guard bands surround ⁇ ing adjacent nMOS and pMOS devices must be the same magnitude, i.e. , 8 microns, in order to prevent Zener breakdown between the guard bands. This can occur because the n-plus guard bands are at the positive supply voltage and the p-plus diffusion guard bands are at ground. As a result of the space between adjacent guard bands valuable space is wasted on the silicon chip substrate resulting in lower yields and greater costs. Disclosure of Invention
  • the p-plus and the n-plus diffusion guard rings are fabri ⁇ cated so that they are juxtapositioned with no space between them.
  • both the p-plus diffusion guard bands as well as the n-plus diffusion guard bands are maintained at the positive supply voltage, Vdd.
  • guard bands continue to function effectively to collect a signifi ⁇ cant amount of injected minority carriers. But because there is no spacing between the adjacent p-plus diffu- sion and n-plus diffusion guard ' bands, valuable sub ⁇ strate area is saved. Further, this improvement requires no additional fabrication steps over the existing guard band design.
  • Figure 1 is a cross-sectional view of a part of a CMOS integrated circuit having conventionally arranged guard band structures.
  • Figure 2 is a schematic diagram of the parasitic bipolar transistors formed in the CMOS integrated circuit of Figure 1.
  • Figure 3 is a cross-sectional diagram of a
  • CMOS circuit having guard bands in accordance with the present invention.
  • OMPI Figure 4 is a schematic diagram of the parasitic bipolar transistors formed in the CMOS circuit of Figure 3.
  • Figure 1 shows a cross-sectional view of a part of a bulk CMOS integrated circuit 10.
  • the indivi ⁇ dual devices are formed in n-type substrate 12.
  • Depicted in Figure 1 is a p-channel MOS (pMOS) transis ⁇ tor 14 and an n-channel MOS (nMOS) device 16.
  • the pMOS 14 includes a p-plus diffusion forming the source 17, gate 18 and another p-plus diffusion area 20 forming the drain.
  • Connected to source 17 is the positive voltage supply Vdd.
  • the voltage supply Vdd is also connected through an n-plus diffused region 21 to substrate 12.
  • the nMOS transistor 16 is formed within a p-well 22 as is well known to those skilled in the art.
  • an n-plus diffusion region 24 constitutes the source
  • another n-plus diffusion region 26 constitutes the drain.
  • the p-well region 22 is connected through a p-plus diffusion region 30 to ground.
  • the source 24 is connected to ground.
  • Figure 2 is a schematic representation of the parasitic bipolar devices which are formed in the CMOS circuit of Figure 1.
  • Parasitic pnp transistor 32 is a lateral device whose emitter is formed by the source 17 of pMOS 18, whose base is formed by the n-plus region 21 and the n substrate 12, and its collector is formed by the p-well 22 and the p-plus region 30 of nMOS 16.
  • a second parasitic device, npn trasistor 34 is also inherently created in the CMOS configuration 10. Its emitter is formed by the source 24 of nMOS 16.
  • the p-plus region 30 and p-well 22 form its base, and its collector is formed by the n substrate 12 and by the n-plus region 21.
  • Normally parasitic transistors 32 and 34 are biased off. However, lateral current flow in the substrate 12 and the p-well 22 can establish potential differences which turn on these parasitic transistors.
  • the substrate resistance, Rsub, and the resistance of the p-well, Rp-well, are shown schematically in Figures 1 and 2.
  • three condi ⁇ tions must be met: (1) sufficient lateral current must be present to forward bias the emitter-base junction of the parasitic transistors 32 and 34; (2) the transistor current gain product, beta npn x beta pnp, must exceed the minimum necessary for regeneration; and (3) the bias supply must be capable of sourcing a current g 3 reater than the holding 3 current.
  • guard rings are used to surround the pMOS and nMOS devices.
  • a p-plus diffusion guard band 36 surrounds the pMOS 14 and a n-plus diffusion guard band 38 surrounds the nMOS 16.
  • the p-plus guard band 36 is connected to ground.
  • the n-plus guard band 38 is connected to the positive voltage supply Vdd.
  • the width of guard rings 36 and 38 must be of the same order of magnitude as the depth of the p-well diffusion 22, or about 8 microns. Addition ⁇ ally, the space 40 between the adjacent guard rings 36 and 38 must be of approximately the same dimensions as the depth of the guard rings. This is to prevent Zener breakdown between the guard rings.
  • the p-plus guard rings 36 is shown as line 36' and the n-plus guard ring 38 is shown as line 38'.
  • the guard band 36 acts as a collector for minority carriers shunting the Rp-well; and guard well 38 acts as a collector of minority carriers to shunt Rsub. As explained, this has the effect of reducing the product of the npn and pnp betas.
  • Figure 3 is a cross-sectional view of a bulk CMOS circuit 10' in accordance with the present invention. Common reference numerals are used in Figure 3 which are found in Figure 1. Unlike Figure 1 , the p-plus diffusion guard band 42 and the n-plus diffusion guard band 44 are located adjacent to each other. The space 40 in Figure 1 is eliminated. To prevent Zener breakdown both the guard bands 42 and 44 are connected to the positive power supply Vdd.
  • n-plus guard band 44 is shown as line 44' and, as in Figure 2, acts to collect minority carriers in a parallel path around Rsub.
  • P-plus guard band 42 is represented by line 42' in Figure 4, connected between the collector of pnp 32 and Vdd.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • the invention is equally applicable to an n-well arrangement.
  • the ' n-plus diffusion guard bands are shown located outside of the p-well. It is also possible for the guard bands to be located within the p-wells or n-wells.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Le verrouillage dans les circuits intégrés CMOS en masse, provoqué par des transistors parasites pnp et npn, est empêché en utilisant des bandes de protection p-plus (42) et n-plus (44) qui sont juxtaposées et connectées à une alimentation de puissance commune (Vdd).Interlocking in mass CMOS integrated circuits, caused by parasitic pnp and npn transistors, is prevented by using protective bands p-plus (42) and n-plus (44) which are juxtaposed and connected to a power supply commune (Vdd).

Description

Description
CMOS Integrated Circuit with Guard. Bands For Latch-Up Protection
Technical Field This invention relates to CMOS integrated
'circuits, and in particular, to bulk CMOS integrated circuits having an improved guard band arrangement to prevent latch-up.
•*
Background Art Latch-up is a potentially serious problem in the operation of CMOS integrated circuits. Latch-up is caused by the formation of parasitic bipolar transistors which are byproducts of both p-channel and n-channel devices. The susceptibility of a CMOS integrated circuit chip to latch-up is a function of the starting material, the processing procedure, and the circuit and chip design techniques.
More particularly, adjacent pMOS and nMOS devices form parasitic npn and pnp devices. Together this constitutes a four layer pnpn path which results in an operation like a silicon controlled rectifier (SCR). Injected minority carrier current may accidently trigger the structure. After triggering, the structure can be turned off only by turning off the power. This triggering can occur when the injected current causes a voltage transient in the circuit that is either above the circuit power supply or below ground.
It is well known that the problem of latch-up is reduced in a CMOS circuit by forcing the product of the parasitic npn and pnp transistor betas to less than one, and by shunting the parasitic resistances with lower resistivity structures. Various process modifica¬ tions to accomplish this are described in an article entitled "Latch-Up Prevention in Bulk P- ell CMOS Circuits" by Jim Lipman, VLSI Design, May-June 1982, page 30. Additionally, various design techniques are used to minimize the latch-up problem for bulk CMOS circuits. These are also described in the article referred to above.
One. esign approach is the use of guard bands or rings. These are p-plus diffusions in the substrate surrounding pMOS transistors, and n-plus diffusion in the p-well surrounding nMOS transistors. The p-plus guard band is tied to ground, and the n-plus is tied to the supply voltage, Vdd. The guard bands reduce the parasitic bipolar transistor beta product by collecting injected minority carriers, and by increasing the distance between adjacent nMOS and pMOS devices.
In order to collect a significant fraction of the injected minority carriers, the width of these guard bands typically must be in the same order of magnitude as the p-well diffusion depth of the nMOS devices. Typically this is about 8 microns. In addition, the spacing between the guard bands surround¬ ing adjacent nMOS and pMOS devices must be the same magnitude, i.e. , 8 microns, in order to prevent Zener breakdown between the guard bands. This can occur because the n-plus guard bands are at the positive supply voltage and the p-plus diffusion guard bands are at ground. As a result of the space between adjacent guard bands valuable space is wasted on the silicon chip substrate resulting in lower yields and greater costs. Disclosure of Invention
It is therefore an object of the invention to provide improved means to prevent latch-up in CMOS circuits. Another object of the invention is to provide improved guard band arrangement to prevent latch-up in bulk CMOS circuits resulting in smaller and more densely packed chip devices.
In accordance with the present invention, the p-plus and the n-plus diffusion guard rings are fabri¬ cated so that they are juxtapositioned with no space between them. To prevent the possibility of Zener breakdown, both the p-plus diffusion guard bands as well as the n-plus diffusion guard bands are maintained at the positive supply voltage, Vdd.
With this configuration, the guard bands continue to function effectively to collect a signifi¬ cant amount of injected minority carriers. But because there is no spacing between the adjacent p-plus diffu- sion and n-plus diffusion guard' bands, valuable sub¬ strate area is saved. Further, this improvement requires no additional fabrication steps over the existing guard band design.
Brief Description of the Drawings Figure 1 is a cross-sectional view of a part of a CMOS integrated circuit having conventionally arranged guard band structures.
Figure 2 is a schematic diagram of the parasitic bipolar transistors formed in the CMOS integrated circuit of Figure 1.
Figure 3 is a cross-sectional diagram of a
CMOS circuit having guard bands in accordance with the present invention.
OMPI Figure 4 is a schematic diagram of the parasitic bipolar transistors formed in the CMOS circuit of Figure 3.
Best Mode for Carrying Out the Invention Figure 1 shows a cross-sectional view of a part of a bulk CMOS integrated circuit 10. The indivi¬ dual devices are formed in n-type substrate 12. Depicted in Figure 1 is a p-channel MOS (pMOS) transis¬ tor 14 and an n-channel MOS (nMOS) device 16. The pMOS 14 includes a p-plus diffusion forming the source 17, gate 18 and another p-plus diffusion area 20 forming the drain. Connected to source 17 is the positive voltage supply Vdd. The voltage supply Vdd is also connected through an n-plus diffused region 21 to substrate 12.
The nMOS transistor 16 is formed within a p-well 22 as is well known to those skilled in the art. In addition to gate 28, an n-plus diffusion region 24 constitutes the source, and another n-plus diffusion region 26 constitutes the drain. The p-well region 22 is connected through a p-plus diffusion region 30 to ground. Similarly, the source 24 is connected to ground.
Figure 2 is a schematic representation of the parasitic bipolar devices which are formed in the CMOS circuit of Figure 1. Parasitic pnp transistor 32 is a lateral device whose emitter is formed by the source 17 of pMOS 18, whose base is formed by the n-plus region 21 and the n substrate 12, and its collector is formed by the p-well 22 and the p-plus region 30 of nMOS 16. A second parasitic device, npn trasistor 34 is also inherently created in the CMOS configuration 10. Its emitter is formed by the source 24 of nMOS 16. The p-plus region 30 and p-well 22 form its base, and its collector is formed by the n substrate 12 and by the n-plus region 21.
Normally parasitic transistors 32 and 34 are biased off. However, lateral current flow in the substrate 12 and the p-well 22 can establish potential differences which turn on these parasitic transistors. The substrate resistance, Rsub, and the resistance of the p-well, Rp-well, are shown schematically in Figures 1 and 2. To sustain the latch-up state, three condi¬ tions must be met: (1) sufficient lateral current must be present to forward bias the emitter-base junction of the parasitic transistors 32 and 34; (2) the transistor current gain product, beta npn x beta pnp, must exceed the minimum necessary for regeneration; and (3) the bias supply must be capable of sourcing a current g3reater than the holding3 current. When betanpn x beta is less than 1 , latch-up is impossible under all conditions. To reduce the parasitic bipolar transistor beta product, guard rings are used to surround the pMOS and nMOS devices. In Figure 1 a p-plus diffusion guard band 36 surrounds the pMOS 14 and a n-plus diffusion guard band 38 surrounds the nMOS 16. The p-plus guard band 36 is connected to ground. The n-plus guard band 38 is connected to the positive voltage supply Vdd. In order to collect a significant fraction of the injected minority carriers, the width of guard rings 36 and 38 must be of the same order of magnitude as the depth of the p-well diffusion 22, or about 8 microns. Addition¬ ally, the space 40 between the adjacent guard rings 36 and 38 must be of approximately the same dimensions as the depth of the guard rings. This is to prevent Zener breakdown between the guard rings.
OMPI In Figure 2 the p-plus guard rings 36 is shown as line 36' and the n-plus guard ring 38 is shown as line 38'. As can be seen, the guard band 36 acts as a collector for minority carriers shunting the Rp-well; and guard well 38 acts as a collector of minority carriers to shunt Rsub. As explained, this has the effect of reducing the product of the npn and pnp betas.
Figure 3 is a cross-sectional view of a bulk CMOS circuit 10' in accordance with the present invention. Common reference numerals are used in Figure 3 which are found in Figure 1. Unlike Figure 1 , the p-plus diffusion guard band 42 and the n-plus diffusion guard band 44 are located adjacent to each other. The space 40 in Figure 1 is eliminated. To prevent Zener breakdown both the guard bands 42 and 44 are connected to the positive power supply Vdd.
The resulting change to the schematic diagram of the parasitic bipolar transistors is shown-in Figure 4. The n-plus guard band 44 is shown as line 44' and, as in Figure 2, acts to collect minority carriers in a parallel path around Rsub. P-plus guard band 42 is represented by line 42' in Figure 4, connected between the collector of pnp 32 and Vdd. By eliminating the space 40 between the guard rings valuable area of the substrate 12 is preserved. This has the effect of increasing yields and of lowering the overall cost of the chip.
While the particular embodiment of CMOS described here utilizes a p-well, the invention is equally applicable to an n-well arrangement. Also, in the embodiment described the' n-plus diffusion guard bands are shown located outside of the p-well. It is also possible for the guard bands to be located within the p-wells or n-wells.

Claims

Claims
1. A CMOS integrated circuit comprising: n-type guard bands surrounding nMOS devices; p-type guard bands surrounding pMOS devices and positioned adjacent said n-type guard bands; and both n-type and p-type guard • • bands biased with the same polarity voltage.
2. A CMOS integrated circuit as in Claim 1 wherein the nMOS devices are formed in p-wells.
3. A CMOS integrated circuit as in Claim 2 wherein the n-type guard bands are located outside of the p-wells.
4. A CMOS integrated circuit as in Claim 2 wherein the n-type guard bands are located within the p-wells.
5. A CMOS integrated circuit as in Claim 1 wherein the pMOS devices are formed in n-wells.
6. A CMOS integrated circuit as in Claim 5 wherein the p-type guard bands are located outside of the n-wells.
7. A CMOS integrated circuit as in Claim 5 wherein the p-type guard bands "are located within the n-wells.
OMPI
8. In a bulk CMOS integrated circuit having guard bands of p-plus diffusions surrounding pMOS transistors and n-plus diffusions surrounding nMOS transistors, wherein the improvement comprises juxtapo- sitioning the respective p-plus and n-plus guard bands and connecting both to a common power supply.
9. A method of preventing latch-up in bulk CMOS integrated circuits caused by parasitic pnp and npn transistors comprising juxtapositioning p-plus and n-plus guard bands and connecting both to a common voltage.
OMPI
EP19830903252 1982-09-20 1983-09-19 Cmos integrated circuit with guard bands for latch-up protection. Withdrawn EP0119260A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42011582A 1982-09-20 1982-09-20
US420115 1982-09-20

Publications (2)

Publication Number Publication Date
EP0119260A1 true EP0119260A1 (en) 1984-09-26
EP0119260A4 EP0119260A4 (en) 1985-10-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP19830903252 Withdrawn EP0119260A4 (en) 1982-09-20 1983-09-19 Cmos integrated circuit with guard bands for latch-up protection.

Country Status (4)

Country Link
EP (1) EP0119260A4 (en)
JP (1) JPS59501766A (en)
IT (1) IT1234924B (en)
WO (1) WO1984001241A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382865A1 (en) * 1989-02-14 1990-08-22 Siemens Aktiengesellschaft Arrangement to reduce latch-up sensitivity in CMOS semiconductor circuits
US5438005A (en) * 1994-04-13 1995-08-01 Winbond Electronics Corp. Deep collection guard ring
KR0131373B1 (en) * 1994-06-15 1998-04-15 김주용 Semiconductor device data output buffer
JP6475093B2 (en) * 2015-06-02 2019-02-27 株式会社東海理化電機製作所 Semiconductor integrated circuit

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JPS5357775A (en) * 1976-11-04 1978-05-25 Mitsubishi Electric Corp Semiconductor ingegrated circuit device
JPS5873147A (en) * 1981-10-27 1983-05-02 Mitsubishi Electric Corp Semiconductor integrated circuit device

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US3955210A (en) * 1974-12-30 1976-05-04 International Business Machines Corporation Elimination of SCR structure
JPS54132179A (en) * 1978-04-06 1979-10-13 Nec Corp Complementary insulating gate field effect semiconductor device
JPS54156491A (en) * 1978-05-30 1979-12-10 Nec Corp Complementary field effect semiconductor device
JPS5939904B2 (en) * 1978-09-28 1984-09-27 株式会社東芝 semiconductor equipment
JPS55141751A (en) * 1979-04-23 1980-11-05 Hitachi Ltd Complementary mis semiconductor device and fabricating method of the same
JPS57100767A (en) * 1980-12-16 1982-06-23 Toshiba Corp Mos type semiconductor device

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JPS5357775A (en) * 1976-11-04 1978-05-25 Mitsubishi Electric Corp Semiconductor ingegrated circuit device
JPS5873147A (en) * 1981-10-27 1983-05-02 Mitsubishi Electric Corp Semiconductor integrated circuit device

Non-Patent Citations (3)

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Title
PATENTS ABSTRACTS OF JAPAN, vol. 2, no. 94, August 5, 1978, page 4370E78; & JP - A - 53 57 775 (MITSUBISHI DENKI K.K.) 25-05-1978 *
PATENTS ABSTRACTS OF JAPAN, vol. 7, no. 166 (E-188)[1311], July 21, 1983; & JP - A - 58 73 147 (MITSUBISHI DENKI K.K.) 02-05-1983 *
See also references of WO8401241A1 *

Also Published As

Publication number Publication date
IT1234924B (en) 1992-06-02
JPS59501766A (en) 1984-10-18
EP0119260A4 (en) 1985-10-01
IT8322918A0 (en) 1983-09-19
WO1984001241A1 (en) 1984-03-29

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