EP0117646A2 - Dispositif de mémoire semi-conductrice avec un circuit de commande à lecture-écriture - Google Patents

Dispositif de mémoire semi-conductrice avec un circuit de commande à lecture-écriture Download PDF

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Publication number
EP0117646A2
EP0117646A2 EP84300557A EP84300557A EP0117646A2 EP 0117646 A2 EP0117646 A2 EP 0117646A2 EP 84300557 A EP84300557 A EP 84300557A EP 84300557 A EP84300557 A EP 84300557A EP 0117646 A2 EP0117646 A2 EP 0117646A2
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EP
European Patent Office
Prior art keywords
writing
transistors
control circuit
reading
bit lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84300557A
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German (de)
English (en)
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EP0117646A3 (en
EP0117646B1 (fr
Inventor
Hidekai Isogai
Isao Fukushi
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Fujitsu Ltd
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Fujitsu Ltd
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Publication of EP0117646A2 publication Critical patent/EP0117646A2/fr
Publication of EP0117646A3 publication Critical patent/EP0117646A3/en
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Publication of EP0117646B1 publication Critical patent/EP0117646B1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Definitions

  • the present invention relates to a semiconductor memory device, more particularly, to a bipolar random access memory (bipolar RAM) using emitter--coupled-logic (ECL) memory cell and peripheral circuits, which can operate on greatly reduced power in both writing and reading operations.
  • bipolar RAM bipolar random access memory
  • ECL emitter--coupled-logic
  • Bipolar RAM's generally comprise an ECL memory cell, consisting of a flip-flop circuit constituted with a pair of multi-emitter transistors and electric elements, and peripheral circuits for controlling writing or reading with the memory cell.
  • bipolar RAM's can be used under high--speed operation, such high-speed operation entails a large current flow in the memory cell and the peripheral circuits. As a result, bipolar RAM's consume large amounts of power. The higher the speed of the writing and reading operation, the greater the power consumption of the bipolar RAM. In this regard, it should be noted that a large unnecessary current flows to the peripheral circuits, particularly during the writing operation.
  • An / of the present invention can provide a bipolar RAM, using an ECL memory cell and a plurality of peripheral circuits, which can operate at a high speed with greatly reduced power consumption and without unnecessary current flowing in the peripheral circuits.
  • a semiconductor memory device used as a bipolar RAM comprising: a plurality of pairs of word lines; a plurality of pairs of bit lines; a plurality of static memory cells, each cell connected between the word lines and the bit lines at intersections thereof; a plurality of constant current sources connected to the bit lines through means for selecting the bit lines; a reading--writing voltage control circuit operatively connected to the bit lines for controlling the potential of each bit line in the reading and writing of data; and a writing current control circuit operatively connected to constant current sources for controlling the current flowing to each bit line in the writing of data to the memory cell.
  • the writing current control circuit operatively connects a constant current source to the reading writing voltage control circuit in the writing of data to the memory cell.
  • the bipolar RAM comprises a decoder circuit DEC, a writing amplifier WA, a reading-writing voltage control circuit RW, a writing current control circuit WC, a reading circuit RC, a bit line selecting circuit BS, constant current sources I W0 , I W1 , IS ' IRO ' I R1 , I CO ' I Cl ' I 0 , I 1 , and I H , and an ECL memory cell CEL.
  • the memory cell CEL is connected between a positive word line W + and a negative word line W and between a bit line B 0 and a bit line B 1 .
  • the memory cell CEL also comprises a pair of NPN transistors T C1 , T C2 constituting a flip-flop circuit and a pair of PNP transistors T C3 ' T C4 used as a load.
  • the positive word line W is connected to the decoder circuit DEC having a word-driver transistor T X .
  • the negative word line W is connected to a holding constant current source I H .
  • a writing command signal WE and a writing data D IN are provided to the writing amplifier WA.
  • the output voltage V W0 , V W1 (at points "a” and "b") of the amplifier WA are set alternately to a high level and a low level corresponding to the input writing data D IN .
  • the output voltages V W0 , V W1 of the amplifier WA are set to a middle voltage level,between the high level and low level obtained when WE is set to a low level.
  • the reading-writing voltage control circuit RW is constituted by two transistors T W1 , T W2 , the bases of which receive output voltages V W1 , V W0 , respectively, the constant current sources I C0 , I C1 , and a pair of transistors T D0 , T D1 , the emitters of which are connected to the bit lines B 0 , B 1 , respectively.
  • the control circuit RW can control the potential of each of bit lines B 0 , B 1 according to the writing command signal WE and the writing data D IN .
  • the writing current control circuit WC is constituted by two diodes D 0 , D 1 for shifting a voltage level, two transistors T W3 , T W4 , and two constant current sources I 0 , I 1 .
  • the control circuit WC can control writing current flowing to the selected bit lines B 0 , B 1 in writing the data to the memory cell CEL.
  • the reading circuit RC is constituted by a pair of transistors T S0 , T S1 , the bases of which are connected to the bit lines B 0 , B 1 , respectively and a sense amplifier SA, detects and amplifies the data which is read out on the bit lines B 0 , B 1 , and provides the output data D out .
  • the bit selecting circuit BS is constituted by two multi-emitter transistors T B0 , T B1 , the collectors of which are connected to the bit lines B 0 , B 1 , respectively.
  • a column selecting signal Vy is applied to the bases of these transistors.
  • the first emitters of the transistors T B0 , T Bl are respectively connected to constant current sources I W0 , I W1 for writing in common with the first emitters of the transistors of other bit selecting circuits (c.f, Fig. 4) connected to other bit lines (c.f, Fig. 4).
  • the second emitters of the transistors T B0 , T B1 are respectively connected to constant current sources I R0 , I RI for reading in common with the second emitters of the transistors of the same other circuits.
  • a transistor TS2 the base . of which receives the column selecting signal Vy , is connected to a common node of the emitters of the transistors T S0 , T S1 and to the constant current source I S via its emitter in common with the emitters of the transistors of the same other circuits.
  • FIG. 2 is a basic circuit diagram of a writing amplifier shown in Fig. 1.
  • the writing amplifier WA is constituted by two pairs of transistors T 61 , T62 and T 63 , T 64 , a pair of diodes D 2 , D 3 , and a constant current source I 2 .
  • the reference voltages V R1 and V R2 are applied to the bases of the transistors T 61 and T 63 , respectively;
  • the writing command signal WE is applied to the base of the transistor T 64 ;
  • the writing data D IN is applied to the base of the transistor T62.
  • the output voltages V W0 and V W1 are provided from the collectors of the transistors T 61 and T62 , respectively.
  • This conventional writing amplifier WA is disclosed in Japanese Examined Patent Publication (Kokoku) No. 57-11178, assigned to Fujitsu Limited. A detailed explanation regarding the operation is therefore omitted.
  • a conventional bipolar RAM requires many constant current sources, such as I C0 , I C1 , I 0 , I 1 , I W0 , I W1 , I RO ' I R1 , and I S .
  • I C0 , I C1 , I 0 , I 1 , I W0 , I W1 , I RO ' I R1 , and I S are constant current sources.
  • the constant current source I W0 or I W1 consumes unnecessary current. for transistors T DO , T D1
  • the independent current source (I CO or I C1 ) mentioned above is eliminated from the reading-writing circuit RW. Instead, the unnecessary current, i.e., the writing current of the side controlled by the writing current control circuit WC, is utilized for controlling the base potential of either the transistor T D0 or T D1 .
  • a bipolar RAM according to an embodiment of the present invention will now be described.
  • the bipolar RAM comprises a decoder circuit DEC, a writing amplifier WA, a reading--writing voltage control circuit RW, a writing current control circuit WC, a reading circuit RC, a bit selecting circuit BS, a plurality of constant current sources I 0 , I 1 , I W0 , I W1 , I R0 , I R1 , I S , and I H , and an ECL memory cell CEL.
  • the memory cell CEL, the writing amplifier WA, the writing current control circuit WC, the reading circuit RC, and the bit line selecting circuit BS are all identical to those in Fig. 1.
  • the reading-writing voltage control circuit RW is constituted by two transistors T W1 , T W2 , the bases of which receive output voltage V W1 , V W0 , respectively, and a pair of transistors T D0 , T D1 , the emitters of which are connected to the bit lines B 0 , B 1 , respectively. There are no longer provided the constant current sources I C0 and I C1 of Fi g. 1. Instead, transistors T W4 , T W3 have their collectors connected to points c, d as shown.
  • the control circuit RW can control the potential of each bit line B 0 , B 1 in accordance with the writing command signal WE and the writing data D IN .
  • the transistors T W3 , T B1 and the transistors T W4 , T B0 constitute so-called current switching W4 B0 through the transistor with the circuits, the current flows through the transistor with the higher base voltage level. Accordingly, since no large current is necessary for the bit lines B 0 , B 1 in the reading operation, the base potentials of the transistors T W3 , T W4 are set to a higher base potential than the potential of V Y .
  • the transistor T C1 turns on, i.e., the base potential of transistor T C1 is higher than that of transistor T D0 , the potential of the bit line B 0 is determined by transistor T C1 in the memory cell CEL. Meanwhile, the potential of the bit line B 1 is determined by the difference output voltage V W1 . Accordingly, a potential/occurs between the bit line B 0 and the bit line B 1 .
  • the potential between the bit line B 0 and the bit line B 1 is detected by the switching circuit, which consists of the transistors T SO , T S1 , T S2 and the constant current source IS , and is provided from the sense amplifier SA as the output data D out .
  • the current flowing from the memory cell CEL to the bit line B 0 is represented by the current i RO which flows to the current source I R0 , since both currents i R0 , i R1 are determined by the condition; i R0 , i R1 ⁇ i W0 , i W1 , in the reading operation. Therefore, it is possible to make the current flowing in the memory cell small compared with the current flowing in the writing operation.
  • V W0 , V W1 are selected so as to satisfy the formula; V W1 - V F ⁇ V Y ⁇ V W0 - V F , where V W0 , V W1 are the output voltages (at points "a" and "b") of the writing amplifier WA, V F is the forward direction voltage drop of the diode D 0 , D 1 , and V Y is the column selecting signal voltage.
  • the current flowing to the constant - current source I W1 flows through the bit line B 1 via the transistor T B1 .
  • the cell transistor T C2 since the base potential of the transistor T D1 is lower than that of the cell transistor T C2 , the cell transistor T C2 turns on according to the current switching circuit function.
  • the base potential of the transistor T DO is higher than that of the cell transistor T C1 , the cell transistor T C1 turns off. Consequently, since a large writing current flows through the transistor T C2 in the memory cell CEL and since a small current is set to flow through the transistor T C2 in the reading operation so as to make the charge accumulation small, as mentioned above, the memory cell CEL can operate quickly in the writing operation.
  • the memory cell can operate quickly in the writing operation based on the two operation procedures.
  • the difference between the present invention and the prior art lies in the connection of the base of the transistor T DO to the collector of the transistor T W3 and the connection of the base of the transistor T D1 to the collector of the transistor T W4 in the reading-writing voltage control circuit RW. Accordingly, the constant current sources I C0 , I C1 are eliminated from the reading-writing voltage control circuit RW.
  • the unnecessary current i.e., one of the writing currents i W0 , i W1
  • the unnecessary current is utilized for controlling the base potential of one that of the transistors T DO or T D1 by connecting/one of the current sources I W0 , I W1 which is unnecessary, to the base of one of the transistors T D0 , T D1 through one of the transistors T W4 , T W3 .
  • part of the conventional base charge flowing from the base of the transistors TDO , T D1 through the current sources I C0 , I C1 as shown in Fig. 1 flows to the constant current sources I W0 , I WI through the transistors T W3 , T W4 ' according to the present invention.
  • FIG. 4 is a block diagram of the overall structure of the bipolar RAM shown in Fig. 3.
  • the memory is constituted by a plurality of static memory cells CEL 11 to CEL .
  • Each memory cell is connected to one of the word line pairs W 1 + , W 1 - to W n + , W n - , and to one of the bit line pairs B 01 , B 1n to B 0n , B 1n .
  • Each of word lines W 1 + to W n + is connected to an X-decoder, and each of word lines W 1 - to W n - is connected to one of holding constant current sources I H1 to I Hn .
  • Each bit line of the pairs B 01 , B 11 to B 0n , B 1n is connected to the reading-writing voltage control circuit RW and to the bit selecting circuit BS.
  • the bit selecting circuit BS is connected to the Y-decoder.
  • Each output of the bit line selecting circuit BS is connected to the constant current sources I W0 , I RO , I S , I W1 , and I R1 respectively. Therefore, these constant current sources I W0 , I R0 , I S , I W1 , T R1 are supplied to only that pair of bit lines which are selected by the bit line selecting circuit BS.
  • each output of the writing current control circuit WC is connected to one of current sources I W0 and I W1 in common with each first emitters of the transistors T B0 , T Bl constituting the bit line selecting circuit BS.
  • Fig. 5 shows another embodiment, which is almost the same as the circuit in Fig. 3, apart from the connection of the diodes D 1 , D 0 . That is, unlike the circuit in Fig. 3, in which the anodes of the diodes D 0 , D 1 are connected to the bases of the transistors T W1 and T W2 , in this embodiment, Fig. 5, the anodes of the diodes D 0 , D 1 are connected to the emitters of the transistors T W1 , T W2 respectively.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
EP84300557A 1983-01-31 1984-01-30 Dispositif de mémoire semi-conductrice avec un circuit de commande à lecture-écriture Expired EP0117646B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP14057/83 1983-01-31
JP58014057A JPS59151386A (ja) 1983-01-31 1983-01-31 半導体記憶装置

Publications (3)

Publication Number Publication Date
EP0117646A2 true EP0117646A2 (fr) 1984-09-05
EP0117646A3 EP0117646A3 (en) 1985-05-22
EP0117646B1 EP0117646B1 (fr) 1987-05-20

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EP84300557A Expired EP0117646B1 (fr) 1983-01-31 1984-01-30 Dispositif de mémoire semi-conductrice avec un circuit de commande à lecture-écriture

Country Status (4)

Country Link
US (1) US4625299A (fr)
EP (1) EP0117646B1 (fr)
JP (1) JPS59151386A (fr)
DE (1) DE3463870D1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0258715A2 (fr) * 1986-08-15 1988-03-09 Nec Corporation Mémoire statique à accès aléatoire d'une construction Bi-CMOS
EP0284665A1 (fr) * 1987-01-15 1988-10-05 International Business Machines Corporation Mémoire statique à semi-conducteurs
EP0310496A2 (fr) * 1987-09-29 1989-04-05 Fujitsu Limited Dispositif de mémoire semi-conductrice synchrone
EP0354950A1 (fr) * 1988-02-11 1990-02-21 Digital Equipment Corp Memoire vive bipolaire a courant d'ecriture variable avec l'etat.
EP0454981A2 (fr) * 1990-04-30 1991-11-06 International Business Machines Corporation Réseau de cellule de mémoire statique à accès aléatoire à émetteur divisé

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703458A (en) * 1985-12-16 1987-10-27 Motorola, Inc. Circuit for writing bipolar memory cells
US4769785A (en) * 1986-06-02 1988-09-06 Advanced Micro Devices, Inc. Writing speed of SCR-based memory cells
JPH02239496A (ja) * 1989-03-13 1990-09-21 Fujitsu Ltd 半導体記憶装置
DE69943247D1 (de) 1998-03-27 2011-04-14 Janssen Pharmaceutica Nv HIV hemmende Pyrimidin Derivate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117790A (en) * 1979-03-02 1980-09-10 Hitachi Ltd Memory circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4272811A (en) * 1979-10-15 1981-06-09 Advanced Micro Devices, Inc. Write and read control circuit for semiconductor memories
JPS6010400B2 (ja) * 1980-10-09 1985-03-16 富士通株式会社 半導体集積回路装置
JPS5766588A (en) * 1980-10-13 1982-04-22 Fujitsu Ltd Semiconductor storage device
JPS6028076B2 (ja) * 1980-12-25 1985-07-02 富士通株式会社 半導体メモリの書込み回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117790A (en) * 1979-03-02 1980-09-10 Hitachi Ltd Memory circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, February 15, 1979, NEW YORK (US) U.BUERKER et al.:"An ECL 100K compatible 1024x4b RAM with 15ns access time.",pages 102-103 * Page 102, right-hand column, liners 9-20; figure 1 * *
PATENTS ABSTRACT OF JAPAN, vol. 4, Nr. 172 (P-38) (654), November 27 1980; & JP-A 55 117 790 (HITACHI SEISAKUSHO K.K.) 10-09-1980 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0258715A2 (fr) * 1986-08-15 1988-03-09 Nec Corporation Mémoire statique à accès aléatoire d'une construction Bi-CMOS
EP0258715A3 (en) * 1986-08-15 1990-07-04 Nec Corporation Static random access memory having bi-cmos construction
EP0523756A2 (fr) * 1986-08-15 1993-01-20 Nec Corporation Mémoire statique à accès aléatoire de construction Bi-CMOS
EP0523756A3 (en) * 1986-08-15 1993-06-09 Nec Corporation Static random access memory having bi-cmos construction
EP0284665A1 (fr) * 1987-01-15 1988-10-05 International Business Machines Corporation Mémoire statique à semi-conducteurs
EP0310496A2 (fr) * 1987-09-29 1989-04-05 Fujitsu Limited Dispositif de mémoire semi-conductrice synchrone
EP0310496A3 (fr) * 1987-09-29 1991-03-13 Fujitsu Limited Dispositif de mémoire semi-conductrice synchrone
EP0354950A1 (fr) * 1988-02-11 1990-02-21 Digital Equipment Corp Memoire vive bipolaire a courant d'ecriture variable avec l'etat.
EP0354950A4 (en) * 1988-02-11 1991-03-20 Digital Equipment Corporation Bipolar ram having state dependent write current
EP0454981A2 (fr) * 1990-04-30 1991-11-06 International Business Machines Corporation Réseau de cellule de mémoire statique à accès aléatoire à émetteur divisé
EP0454981A3 (en) * 1990-04-30 1993-01-27 International Business Machines Corporation A static random access split-emitter memory cell array

Also Published As

Publication number Publication date
EP0117646A3 (en) 1985-05-22
JPS59151386A (ja) 1984-08-29
EP0117646B1 (fr) 1987-05-20
DE3463870D1 (en) 1987-06-25
US4625299A (en) 1986-11-25
JPH0252360B2 (fr) 1990-11-13

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