EP0076215A2 - Masque d'ombre pour arrachement - Google Patents

Masque d'ombre pour arrachement Download PDF

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Publication number
EP0076215A2
EP0076215A2 EP82401747A EP82401747A EP0076215A2 EP 0076215 A2 EP0076215 A2 EP 0076215A2 EP 82401747 A EP82401747 A EP 82401747A EP 82401747 A EP82401747 A EP 82401747A EP 0076215 A2 EP0076215 A2 EP 0076215A2
Authority
EP
European Patent Office
Prior art keywords
layer
portions
water
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP82401747A
Other languages
German (de)
English (en)
Other versions
EP0076215B1 (fr
EP0076215A3 (en
Inventor
William I. Lehrer
John M. Vincak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp, Fairchild Semiconductor Corp filed Critical Fairchild Camera and Instrument Corp
Publication of EP0076215A2 publication Critical patent/EP0076215A2/fr
Publication of EP0076215A3 publication Critical patent/EP0076215A3/en
Application granted granted Critical
Publication of EP0076215B1 publication Critical patent/EP0076215B1/fr
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Definitions

  • This invention relates to the manufacture of devices by photofabrication and particularly to a process for forming masks employed in such manufacture.
  • a film or layer of material is formed into a predetermined configuration on a selected surface. For example, after forming an integrated circuit on a surface of a semiconductor chip, it is necessary to make electrical contact with the numerous elements or regions of the circuit. Such contact may be accomplished by forming a predetermined configuration of contacting material over the surface of the integrated circuit, the contacting material being separated from the surface by a layer of dielectric.
  • a predetermined configuration in the form of a narrow cut in a passivating layer of material for example silicon monoxide
  • a predetermined configuration in the form of a narrow cut in a passivating layer of material, for example silicon monoxide, may be made incident to forming a device in or on a substrate.
  • independent masks that is, masks not on the surface of an actual device, are formed for employment in exposing and processing of an actual device.
  • Each of these various applications may involve the formation of a film or layer of material into a predetermined configuration.
  • Lifting processes involve depositing the film of material partially upon a surface and partially upon a lifting material which is formed in a pattern upon the surface. The lifting material is then removed along with the film material deposited thereover leaving a desired pattern of the film material on the surface.
  • the film material When a film material is applied to the lifting material and the exposed portion of the surface, the film material takes a continuous form. Thus, when the lifting material is removed, the layer of film material must be broken. Breaking of the film material creates problms not only in its precise definition but also in it functional characteristics.
  • the present invention relates to a method for forming a lift-off shadow mask which permits formation of a film material of precisely-defined predetermined configuration.
  • One aspect of the invention is attained by a method for forming a predetermined configuration of a film material comprising: forming a layer of a first material on a surface; forming a layer of a second material on said layer of first material, said first material having an etch rate greater than that of said second material when said first and second materials are exposed to a common etchant; etching portions of said second material and underlying portions of said first material utilizing a common etchant to expose portions of said surface; forming a layer of film material on said exposed portions of said surface and on remaining portions of said layer of second material; and removing remaining portions of said first material such that overlying second material and film material thereon are also removed.
  • Fig. 1 shows a substrate 10 of semiconductor material.
  • a layer.12 of thermal oxide having an upper surface 13 is formed on the substrate 10.
  • a layer 14 of germanium dioxide is formed on the surface 13 followed by the formation of an overlaying layer 16 of silicon dioxide layer 14 and silicon dioxide layer 16 are formed by chemical vapor deposition.
  • the germanium dioxide layer 14 is deposited in a conventional CVD reactor which is maintained at about 400° C. Nitrogen gas is introduced to the reactor at a flow rate of about 40 liters/min. Oxygen is introduced to the reactor at a flow rate of about 1.5 liters/min. Germane is introduced to the reactor at a flow rate of about 15 cc/min, that is, such that the ratio of oxygen to germane is about 100:1. Germanium dioxide layer 14 is deposited on surface 13 at a rate of about 200 A°/min to a thickness of about 7500 A°.
  • silicon dioxide layer 16 is deposited by maintaining the reactor at about 400°C and introducing nitrogen gas at a flow rate of about 40 liters/min. Oxygen is introduced to the reactor at a flow rate of about 1.5 liters/min. Silane is introduced to the reactor at a flow rate of about 15 cc/min, that is, such that the ratio of oxygen to silane is about 100:1. Silicon dioxide layer 16 is deposited on the germanium dioxide layer 14 at a rate of about 1000 A°/min to a thickness of about 2500 A°.
  • a patterned layer of photoresist is formed as shown in Fig. 3.
  • the photoresist material may be a photoresist such as AZ.
  • the photoresist is applied in the form of a continuous layer by standard photoresist coating apparatus.
  • the photoresist is then exposed and developed according to well-known photoengraving techniques leaving an image 18 of the photoresist material such as shown in Fig. 3.
  • germanium dioxide exhibits 5 to 10 time the etch rate of undoped silicon dioxide. Therefore, it is possible to deposit the layered structure shown in Fig. 2, mask with photoresist and then dry etch in a CF 4 -based plasma reactor to produce the undercut shadow-mask structure shown in Fig. 4. According to the preferred method, the silicon dioxide and germanium dioxide are etched in an IPC Barrel Etcher utilizing a 4% CF 4/ 0 2 plasma at about 0.4 Torr and about 300-400 watts.
  • the photoresist 18 is then removed, preferably by "ashing" in an O 2 plasma, to expose the underlying silicon dioxide layer 16 as shown in Fig. 5.
  • the film material 20 to be patterned is then deposited upon the exposed surface of silicon dioxide layer 16 and upon the exposed portions of the surface 13 of the thermal oxide layer 12. As shown in Fig. 6, in the preferred embodiment, following the deposition of film material 20, a gap or pocket exists beneath the undercut portion of silicon dioxide layer 16. The entire structure is then immersed in water. Since germanium dioxide produced in the above-described manner is completely soluble in water which silicon dioxide is insoluble in water, the germanium dioxide layer is dissolved carrying with it the overlying silicon dioxide and leaving the patterned film material 20 as shown in Fig. 7.
  • the lift-off film that is, silicon dioxide/germanium dioxide
  • the materials used are "clean dielectrics" and will not cause any contamination even if used at high temperature.
  • the lift-off solvent is water which is a distinct advantage.
  • germanium dioxide and silicon dioxide are compatible oxide materials, mixtures can be made to vary the degree of etch rate and the geometry of the indentation.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
EP82401747A 1981-09-28 1982-09-28 Masque d'ombre pour arrachement Expired EP0076215B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US306116 1981-09-28
US06/306,116 US4387145A (en) 1981-09-28 1981-09-28 Lift-off shadow mask

Publications (3)

Publication Number Publication Date
EP0076215A2 true EP0076215A2 (fr) 1983-04-06
EP0076215A3 EP0076215A3 (en) 1984-11-14
EP0076215B1 EP0076215B1 (fr) 1989-02-01

Family

ID=23183888

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82401747A Expired EP0076215B1 (fr) 1981-09-28 1982-09-28 Masque d'ombre pour arrachement

Country Status (4)

Country Link
US (1) US4387145A (fr)
EP (1) EP0076215B1 (fr)
CA (1) CA1187211A (fr)
DE (1) DE3279430D1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0223032A2 (fr) * 1985-11-18 1987-05-27 International Business Machines Corporation Procédé pour la formation d'ouvertures de masque submicronique utilisant les techniques de décollage et utilisation d'écarteurs accolés
DE3609274A1 (de) * 1986-03-19 1987-09-24 Siemens Ag Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes
WO2018048742A1 (fr) * 2016-09-02 2018-03-15 The Board Of Trustees Of The Leland Stanford Junior University Procédé de formation de motifs lithographique sur des matériaux sensibles

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4572765A (en) * 1983-05-02 1986-02-25 Fairchild Camera & Instrument Corporation Method of fabricating integrated circuit structures using replica patterning
ATA331285A (de) * 1985-11-13 1988-11-15 Ims Ionen Mikrofab Syst Verfahren zur herstellung einer transmissionsmaske
US4711701A (en) * 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
US5140396A (en) * 1990-10-10 1992-08-18 Polaroid Corporation Filter and solid state imager incorporating this filter
US5059500A (en) * 1990-10-10 1991-10-22 Polaroid Corporation Process for forming a color filter
US5923995A (en) * 1997-04-18 1999-07-13 National Semiconductor Corporation Methods and apparatuses for singulation of microelectromechanical systems
US6444402B1 (en) 2000-03-21 2002-09-03 International Business Machines Corporation Method of making differently sized vias and lines on the same lithography level
US6420206B1 (en) 2001-01-30 2002-07-16 Axsun Technologies, Inc. Optical membrane singulation process utilizing backside and frontside protective coating during die saw
EP1510861A1 (fr) * 2003-08-26 2005-03-02 Sony International (Europe) GmbH Méthode pour créer des structures dans des matériaux organiques ou dans des composites organiques-inorganiques
US7709274B1 (en) * 2007-05-30 2010-05-04 The United States Of America As Represented By The Secretary Of The Navy Method for forming an RuOx electrode and structure
US8652339B1 (en) * 2013-01-22 2014-02-18 The United States Of America, As Represented By The Secretary Of The Navy Patterned lift-off of thin films deposited at high temperatures
US20170205706A1 (en) * 2014-07-07 2017-07-20 Planxwell Ltd. A Suspended Structure Made of Inorganic Materials and a Method for Manufacturing Same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1203341A (en) * 1967-01-09 1970-08-26 Ibm Improvements in or relating to etching of openings in films
FR2310633A1 (fr) * 1975-05-09 1976-12-03 Ibm Procede pour former des configurations de films desirees selon les techniques additives
US4108717A (en) * 1974-07-08 1978-08-22 Siemens Aktiengesellschaft Process for the production of fine structures consisting of a vapor-deposited material on a base
US4132586A (en) * 1977-12-20 1979-01-02 International Business Machines Corporation Selective dry etching of substrates
US4224361A (en) * 1978-09-05 1980-09-23 International Business Machines Corporation High temperature lift-off technique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3669661A (en) * 1970-03-06 1972-06-13 Westinghouse Electric Corp Method of producing thin film transistors
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1203341A (en) * 1967-01-09 1970-08-26 Ibm Improvements in or relating to etching of openings in films
US4108717A (en) * 1974-07-08 1978-08-22 Siemens Aktiengesellschaft Process for the production of fine structures consisting of a vapor-deposited material on a base
FR2310633A1 (fr) * 1975-05-09 1976-12-03 Ibm Procede pour former des configurations de films desirees selon les techniques additives
US4132586A (en) * 1977-12-20 1979-01-02 International Business Machines Corporation Selective dry etching of substrates
US4224361A (en) * 1978-09-05 1980-09-23 International Business Machines Corporation High temperature lift-off technique

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0223032A2 (fr) * 1985-11-18 1987-05-27 International Business Machines Corporation Procédé pour la formation d'ouvertures de masque submicronique utilisant les techniques de décollage et utilisation d'écarteurs accolés
EP0223032A3 (fr) * 1985-11-18 1990-06-27 International Business Machines Corporation Procédé pour la formation d'ouvertures de masque submicronique utilisant les techniques de décollage et utilisation d'écarteurs accolés
DE3609274A1 (de) * 1986-03-19 1987-09-24 Siemens Ag Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes
WO2018048742A1 (fr) * 2016-09-02 2018-03-15 The Board Of Trustees Of The Leland Stanford Junior University Procédé de formation de motifs lithographique sur des matériaux sensibles
US10581003B2 (en) 2016-09-02 2020-03-03 The Board of Trustee of the Leland Stanford Junior Universtiy Method for lithograghic patterning of sensitive materials

Also Published As

Publication number Publication date
US4387145A (en) 1983-06-07
DE3279430D1 (en) 1989-03-09
EP0076215B1 (fr) 1989-02-01
CA1187211A (fr) 1985-05-14
EP0076215A3 (en) 1984-11-14

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