EP0052236A1 - Générateur de son - Google Patents

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Publication number
EP0052236A1
EP0052236A1 EP81108368A EP81108368A EP0052236A1 EP 0052236 A1 EP0052236 A1 EP 0052236A1 EP 81108368 A EP81108368 A EP 81108368A EP 81108368 A EP81108368 A EP 81108368A EP 0052236 A1 EP0052236 A1 EP 0052236A1
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EP
European Patent Office
Prior art keywords
circuit
tone
input
npn transistor
frequency
Prior art date
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Granted
Application number
EP81108368A
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German (de)
English (en)
Other versions
EP0052236B1 (fr
Inventor
Bruno Dipl.-Ing. Scheckel
Ernst Dipl.-Ing. Wittenzellner
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Siemens AG
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Siemens AG
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Priority claimed from DE19803043505 external-priority patent/DE3043505A1/de
Priority claimed from DE19803050148 external-priority patent/DE3050148A1/de
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0052236A1 publication Critical patent/EP0052236A1/fr
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Publication of EP0052236B1 publication Critical patent/EP0052236B1/fr
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/0207—Driving circuits
    • B06B1/0223—Driving circuits for generating signals continuous in time
    • B06B1/0269—Driving circuits for generating signals continuous in time for generating multiple frequencies
    • B06B1/0276—Driving circuits for generating signals continuous in time for generating multiple frequencies with simultaneous generation, e.g. with modulation, harmonics
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/18—Selecting circuits
    • G10H1/26—Selecting circuits for automatically producing a series of tones

Definitions

  • the invention relates to a tone generator with a semiconductor circuit for automatically generating a tone sequence consisting of at least two different tones by means of an electro-acoustic transducer (loudspeaker) controlled by the semiconductor circuit, in which the semiconductor circuit has an RC oscillator and at least one frequency divider acted upon by it contains.
  • the aim here is to improve the sound quality and, above all, to reduce the monolithically non-integrable part of the circuit compared to the options available to date.
  • the solution proposed according to the invention is that a bistable switch to be activated by a start signal is provided for activating a voltage stabilization circuit, and that the voltage supplied by the voltage stabilization circuit is provided on the one hand for activating the RC oscillator and on the other hand for activating the other circuit parts , and that, finally, as further circuit parts in addition to the frequency divider acted upon by the oscillator, a circuit controlled by the first divider output for the general sequence control and also by both the sequence control and by that of the to generate Outputs to be applied to the corresponding tone frequencies corresponding to the tone sequence and one digital-to-analog converter each assigned to the individual tone frequencies supplied by the frequency divider are provided, the outputs of the digital-to-analog converter being connected to the acoustic converter, in particular with the interposition of an amplifier.
  • an RC oscillator 0 is initially provided which is acted upon by a frequency-determining timing element via the two control inputs 5 and 6 *.
  • the frequency-determining timing element consists of. the resistor R bridging the two connections 5 * and 6 * and the capacitor C connecting the connection 5 of the oscillator 0 to the reference potential U2.
  • the square-wave pulses emitted by the oscillator 0 on the one hand reach a frequency divider TT which, in a known manner, consists of a number of flip-flop cells connected in series with one another with respect to their signal-carrying outputs and inputs and thus corresponds to a binary synchronous or asynchronous counter.
  • An output I, an output II and an output III of each of a selected flip-flop of the divider chain TT each provide a tone frequency of the tone sequence to be generated, that is to say a square-wave oscillation of the frequency corresponding to the respective tone derived by frequency division from the mother frequency supplied by the oscillator 0 Levels correspond to the logic "0" and "1" states.
  • circuit parts G1, G2, G3 are also each one second input from the audio frequency divider TT controlled via the sequence control AS with practically the same frequency as the input of the relevant circuit part of the modulator Mo.
  • Each of these circuit parts G1, G2, G3 of the modulator Mo controls a digital-to-analog converter DA1 or DA2 or DA3, the outputs of which are used to control the loudspeaker L via a common mixing stage M and an amplifier V connected downstream thereof.
  • the amplifier V can also be influenced directly by the sequence control with regard to its degree of amplification.
  • a stabilization circuit ST has the task of stabilizing the operating voltage to be given to the various circuit parts and then passing it on to the other circuit parts. It receives the supply voltage UB via the connections 2 * and 4 * already introduced above of the entire circuit of the tone generator To1 and To2, which, as already emphasized, is shown in FIG. 2 in the block diagram and can be easily implemented monolithically. Another terminal 6 * * provides the roughnessde to the various components of the circuit stabilized DC voltage with the terminal. 4
  • This key position of the stabilization circuit ST explains why the start signal to be applied to the input 1 * of the tone generator, as can be seen from FIG. 2, initially acts on the stabilization circuit ST.
  • a switch Sch provided by a flip-flop with reset input is provided as an intermediary, which in turn is controlled by the sequence control in two respects.
  • the switch Sch is z. B. upright by pressing the push button Dt or by another during the duration of the gong start signal St to be obtained is set. But it may also be that the flip-flop Sch due to a z. B. from another circuit part originating interference signal in the operating state.
  • the sequence controller AS polls the logic state at the inputs of the switch Sch again after a so-called dead time Tz has elapsed.
  • the dead time Tz is z. B. 10 msec. If the start signal St is still pending at the inputs of the switch Sch, the circuit, ie the sound signal to be applied to the second inputs of the circuit parts G1, G2 and G3 of the modulator Mo, is released. Otherwise, the sequential control system AS issues a reset signal Re to the input switch Sch, so that it is tilted back into the initial state.
  • the operating state of the stabilization circuit ST, the oscillator 0 and the audio frequency divider TT also changes, which are then switched off automatically.
  • this first generates a general reset signal RES which, via the sequence control AS, ensures that all circuit parts are in the initial state required for the generation of the tone sequence or pass into it . Details regarding the operating sequence of the circuit are given in the description of a circuit implementation according to FIGS. 3 and 4 which is preferably to be used.
  • the circuit shown in FIG. 3 relates to a bipolar configuration of a tone generator to be implemented monolithically according to the invention according to FIG. 2 and contains the stabilization circuit ST, the oscillator 0 and the low-frequency amplifier V of the system shown in FIG. 2, while in
  • Fig. 4 shows an embodiment for the audio frequency divider TT, for the sequence control AS and for the modulator circuit Mo, etc. required, d. H. the components of the circuit given by logic gates or flip-flops is brought.
  • the Z. B. supplied by a push button Dt start signal is connected to the inputs 2 * and 1 * of the circuit of the audio frequency generator. It initially affects the switch stage SCH upstream of the stabilization stage ST.
  • This essentially consists of the two npn transistors 4 and 5 and the pnp transistor 8, which together form a flip-flop.
  • the input 1 * of the circuit to be acted upon by the pushbutton Dt is connected to the cathode of a diode 1, the ground of which is at the reference potential, ie is connected to the terminal 4 * of the circuit.
  • input 1 * is connected via resistor 2 to the base of npn transistor 4, which is also connected via resistor 3 to the reference potential.
  • the emitter of the NPN transistor 4 and the emitter of the NPN transistor 5 are also at the reference potential, while their collectors are connected to the terminal 2 * of the circuit via a voltage divider 6, 7.
  • the dividing point between the two resistors 6 and 7 forming the voltage divider is connected directly to the base of the pnp transistor 8.
  • the collector of the pnp transistor 8 is connected via the resistor 9 to the base of the second npn transistor of the switch SCH, that is to say the transistor 5, which is also connected via the resistor 10 to the reference potential, that is to say the terminal 4 * of the circuit, and finally also via a circuit point a, to be described later, is controlled by the flip-flop N4, N5 shown in FIG. 4.
  • the emitter of the PNP transistor 8 * is set to the positive pole of the supply-voltage ource UB, that is to the terminal 2 of the circuit.
  • the stabilization circuit ST is activated by the switch SCH via the emitter-collector path of the pnp transistor 8.
  • the voltage stabilization circuit ST contains, as an essential component, the two npn transistors 15 and 16, which are combined to form a Darlington stage, and the zener diode 13 for specifying the setpoint for the direct voltage to be supplied to the further circuit.
  • the collectors of the two npn transistors 15 and 16 are at the emitter of the pnp transistor 8 of the circuit part SCH and thus at the connection 2 *. Furthermore, the base of the one npn transistor 15 is connected via a resistor 11 to the collector of the pnp transistor 8 and to the anode of the diode 12 and via a resistor 14 to its own emitter, while the anode of the said diode 12 is connected to the Cathode of the Zener diode 13 and is connected to the terminal 4 * and thus to the reference potential. Finally, the emitter of the npn transistor 15 lies at the base of the second npn transistor 16 of the stabilization circuit.
  • the npn transistor 16 which is connected as an emitter follower, serves in a manner to be described for the power supply of further circuit parts.
  • the emitter of the npn transistor 15 and thus the base of the npn transistor 16 of the stabilization circuit ST is connected to the connection 6 * of the circuit and thus, as can be seen in FIGS. 1 and 5, to the resistor R1 of the oscillator . frequency determining timing element.
  • the oscillator an RC oscillator 0 is applied via the inputs 4 * , 5 * and 6 * . It contains fourteen npn transistors and a diode as well as resistors. Specifically, the terminal 4 * carrying the reference potential is first connected directly to the cathode of the diode 19 and to the emitter of the npn transistor 20, while the anode of the diode 19 is at the base of the said npn transistor 20 and a resistor 1 ö on the emitter of another npn transistor 17, the collector of which is connected directly and the base of which is connected via a resistor 38 to the terminal 6 * of the circuit.
  • the npn transistor 20 already mentioned in the last paragraph is connected to its collector and the resistor 21 to the base of a third npn transistor 23, the emitter of which is also connected to the reference potential 4 *. lies and whose collector is connected on the one hand via the resistor 28 to the terminal 6 and thus to the emitter of the npn transistor 15 in the stabilization circuit ST, while on the other hand a direct connection between the collector of the third npn transistor 23 and the base of a fourth npn -Transistor 24 exists.
  • the emitter of the fourth NPN transistor 24 is in turn connected to the reference potential, that is to the terminal 4 * , while its collector is connected to the bases of a fifth and a sixth NPN transistor 42 and 47 via a resistor 41 and 46, respectively.
  • the emitters of the two last-mentioned npn transistors 42 and 47 are also at the reference potential, so that these transistors are also operated in an emitter circuit.
  • the collector of the fifth npn transistor 42 leads via a resistor 43 to the base of two further npn transistors 45 and 36, while the collector of the sixth npn transistor 47 via a circuit point c in a manner to be described below for signaling for the frequency divider TT of the tone generator circuit is provided.
  • the collector of the seventh npn transistor 45 whose base is connected via the resistor 43 to the collector of the fifth npn transistor 42 of the oscillator 0 that is, its collector is directly connected to the stabilized voltage and thus to terminal 6 * of the circuit.
  • the eighth npn transistor 36 also introduced in the last paragraph in connection with the fifth transistor 42, lies on the one hand with its collector on the base of the second npn transistor 17 already introduced above and on the other hand via a resistor 38 at the terminal 6 * carrying the stabilized voltage .
  • the collector of the eleventh npn transistor 27 is located directly on the terminal 6 * of the circuit carrying the stabilizing voltage, while the emitter of this transistor 27 is connected via a resistor 26 to the collector of the first n p n transistor 20 of the oscillator, via the one already mentioned Resistor 21 is connected to the base of the third npn transistor 23 and via a further resistor 22 to the base of a twelfth npn transistor 25 which is also connected to its emitter at the reference potential 4 *.
  • the collector of this twelfth npn transistor 25 leads via a resistor 29 to a circuit node which is connected on the one hand via a resistor 30 to the reference potential and via a resistor 31 to the terminal 6 * of the circuit carrying the stabilizing voltage, while on the other hand said node is located directly at the base of the tenth NPN transistor 37, that is to say the second transistor of the differential amplifier 36, 37.
  • the seventh NPN transistor 45 which is already in the top was introduced in connection with the fifth NPN transistor 42, (as already mentioned) is connected to the terminal 6 * with its collector. It should also be noted with regard to this transistor 45 that its emitter is connected via a resistor 44 to the base of a ninth NPN transistor 48, the emitter of which is also connected directly to the reference potential, that is to the terminal 4 * of the circuit, while Collector is connected via a node d in a manner to be described to the AND gate U13 shown in FIG. 4 and other circuit parts.
  • a constant current source is provided to supply power to the differential amplifier formed from the eighth and tenth npn transistors 36 and 37.
  • This consists of a thirteenth npn transistor 34, the emitter of which is connected to the reference potential via a resistor 35 and the collector and base of which are connected via a resistor 40 to the terminal 6 * of the circuit to which the stabilized voltage is applied, in combination with a fourteenth npn transistor 32.
  • the emitter of this fourteenth npn transistor 32 is in turn connected to the reference potential via a resistor 33, its base with the base and the collector of the thirteenth transistor 34 and its collector forming the output of the current source to the emitter of the eighth and the tenth npn transistor, that is to say the transistors 36 and 37 forming the differential amplifier.
  • the base of the eighth npn transistor 36 and thus the control input of said differential amplifier is connected directly to the terminal 5 * of the circuit and thus via the capacitor C1 when using the circuit shown in FIG. 1 to the reference potential , that is the negative pole of the DC voltage source UB.
  • the differential amplifier V takes up the lower part of the circuit diagram shown in FIG. 3. It receives its operating voltage on the one hand from the emitter of the NPN transistor 15 from the stabilization circuit ST and on the other hand from the supply connection 4 * of the overall circuit. Its circuit will now be briefly described.
  • the stabilization input 6 * of the circuit is connected to the emitter of a first pnp transistor 65 and a second pnp transistor 66 of the amplifier V, which are directly connected to their base connections, the collector base path of the second pnp transistor 66 also being short-circuited.
  • the collectors of the two pnp transistors are connected to the collector of a first npn transistor 64 and a second npn transistor 67, the emitters of which are connected to one another to form a differential amplifier and are connected to the collector of a third npn transistor 68.
  • the third NPN transistor 68 is connected to a fourth NPN transistor 69 to form a current mirror, the fourth transistor 69 being connected as a diode by short-circuiting its base-collector path and the emitters of both transistors 68 and 69 being connected to the reference potential, i.e. the 4 * connection. Finally, the base connections of transistors 68 and 69 are connected via resistor 70 to connection 6 * of the circuit carrying the stabilized voltage.
  • the base of the second NPN transistor 67 in the differential amplifier 64, 67 is located directly at the terminal 7 * of the overall circuit, which, as already mentioned in the description of FIG. 2, for controlling further circuit parts, for. B. the second tone frequency generator circuit To2. Furthermore, the base of the second npn transistor 67 is connected to the mixer M, al so the signal used to control the loudspeaker L is acted upon and thus serves as an amplifier input.
  • the base of the transistor 67 is connected via the resistor 71 to the emitter of a fifth npn transistor 73, which with its emitter on the one hand via the resistor 72 to the reference potential, with its collector at the terminal 6 * of the circuit which carries the stabilized voltage and with its base is connected to the reference potential 4 * via a voltage divider 75, 74.
  • a resistor 76 also connects the collector and the base of the fifth npn transistor 73.
  • the dividing point of the voltage divider 74, 75 leads to the base of a sixth npn transistor 60, the collector of which is also connected to the stabilized voltage terminal 6 * of the circuit while its emitter is connected via a resistor 62 to the base of the first npn transistor 64 forming the reference input of the differential amplifier 64, 67 and is also connected to the reference potential via a resistor 61.
  • a seventh npn transistor 59 has its emitter connected to the reference potential 4 * and its collector to the collector of the first pnp transistor 65 and the collector of the first n p n transistor 64. Finally, the base of the first NPN transistor 64 and thus the reference input of the differential amplifier 67, 64 is connected via a resistor 63 to the output 3 * of the low-frequency amplifier and thus to the circuit.
  • the collectors of the first pnp transistor 65 and the two npn transistors 64 and 59 are also at the base of an eighth npn transistor 50.
  • the base of the seventh npn transistor 59 is on the one hand via a circuit point b in a manner to be described by the Controlled flip-flop N4, N5 shown in Fig. 4. It is also connected to the emitter via a resistor 58 of the transistor 16, which forms an output of the stabilization circuit and has already been described.
  • the collector of the eighth npn transistor 50 is likewise located directly at the emitter of this transistor 16.
  • the collector of a ninth npn transistor 49 whose base is connected to the emitter of the eighth NPN transistor 50 and its emitter is connected to the terminal forming the output 3 * of the amplifier V.
  • the emitter of the eighth npn transistor 50 and the base of the ninth npn transistor 49 lie on the collector of a tenth npn transistor 51, the base of which is short-circuited to its own collector and the emitter of which is connected to its own base via a resistor 52.
  • An eleventh npn transistor 56 with a short-circuited emitter base path is connected with its emitter to the reference potential 4 * and also to the base of a twelfth npn transistor 55, the emitter of which is also at the reference potential 4 * .
  • the collector of the eleventh npn transistor 56 is connected to the emitter of the transistor 16 in the stabilization circuit ST by means of a resistor 57, while the collector of the twelfth npn transistor 55 is connected on the one hand to the emitter of the tenth npn transistor 51 and on the other hand to the base a third pnp transistor 53 is connected directly.
  • the collector of the third pnp transistor 53 lies at the base of a thirteenth npn transistor 54, the emitter of which has the reference potential 4 * and the collector thereof, together with the collector of the third pnp transistor 53 at the connection 3 * of the circuit, ie at the signal output of the amplifier V is.
  • the circuit point c already mentioned in connection with the npn transistor 47 of the oscillator is, as can be seen from FIG. 4, connected to the signal input of three frequency dividers FT1, FT2, FT3 via an inverter I1.
  • the oscillator 0 is tuned so that it, for example provides a frequency of 13.2 kHz. This frequency is used to derive the frequencies 440 Hz, 550 Hz and 660 Hz in the frequency dividers, which are then connected to one of the outputs I or II or III of the frequency divider circuit TT.
  • the divider output delivering the desired frequency of the divider FT1 or FT2 or FT3 provided in the divider circuit TT is connected to the set input S of a flip-flop F1 or F2 or F3, the non-inverted output Q of which is one of the outputs I or II or III forms.
  • the two first dividers FT1 and FT2 are connected with their divider outputs to an input of a NAND gate N1 or N2, the output of which is connected to the reset input R of the relevant divider stage.
  • the third divider FT3, however, has no NAND gate.
  • the divider FT1 together with the flip-flop F1 and the NAND gate N1 forms a 1:30 divider stage.
  • the divider FT2, the NAND gate N2 and the flip-flop F2 together form a 1:24 divider stage and the divider FT3 forms a 1:20 divider stage with the flip-flop F3.
  • the flip-flops F1, F2, F3 provided in the circuit and the flip-flops to be mentioned are preferably designed as D-flip-flops, the inverting output Q of which is fed back to the data input (D) of the flip-flop in question.
  • the other input of this AND gate U13 is through the inverting output Q of the flip-flop F10 to be mentioned.
  • the output of this AND gate U13 leads to the set inputs S of the flip-flops F4, F5, F6, F7 and to the reset inputs R of the flip-flops F8, F9, F10, F11 and F12.
  • the output of the AND gate U13 is also connected to an output of a fourth 1:16 frequency divider FT4 and a fifth 1:16 frequency divider FT5 and finally controls a NAND gate N5, which can be seen in FIG a second NAND gate N4 is cross-coupled to form an RS flip-flop N4, N5.
  • the free input of the other NAND gate N4 of the multivibrator N4, N5 is controlled by an inverter 13 from a second output of the fourth frequency divider FT4.
  • the signal outputs of the two cross-coupled NAND gates N4 and N5 forming the Q or Q output of the RS flip-flop N4, N5 are connected to the circuit points a and b already mentioned in connection with FIG. 3.
  • the output of the NAND gate N4 represents the Q output of the RS flip-flop and is connected to the base of the npn transistor 59 of the differential amplifier V via the node b.
  • the output of the NAND gate N5 forms the non-inverting output, i.e. the Q output of the flip-flop, and leads via the node a to the base of the npn transistor 5 and thus to the reset input of the flip-flop 4, 5 in the switching part SCH.
  • the first audio signal output I of the frequency divider circuit is connected to the clock input t of the fourth frequency divider FT4, the output of which is connected to the clock input t of the fifth divider FT5.
  • the output of the fifth divider FT5 is connected via an inverter 14 to the clock input t of the fourth D flip-flop F4 of the circuit.
  • the D flip-flops F4 to F7 form a chain, the non-inverting output Q of the preceding stage being connected to the clock input t of the following stage.
  • the set inputs S of these D flip-flops F4 to F7 are connected in parallel with one another and with the reset inputs R D flip-flop cells F8 to F11 connected.
  • the Q output of the last flip-flop, with its set input S at the output of the AND gate U13, that is to say of the flip-flop F7, is connected to the t input of the D flip-flop F9 and to the input of a modulator Mo associated AND gate U4 connected.
  • the Q output of the D flip-flop F7 is connected once to the clock input (ie the t input) of the D flip-flop F8 and to an input of an AND gate U12 belonging to the modulator Mo.
  • the Q output of the D flip-flop F8 controls one input each of four AND gates U9, U10, U11 and U12 of the modulator Mo.
  • the Q output of the flip-flop F8 is at the clock input t of the flip-flop F10, whose Q output is connected to one input of AND gate U13 in the manner already described, while the non-inverting output of flip-flop F10 is no longer used.
  • flip-flop F9 While its inverting output Q is provided for controlling one input each of the four AND gates U1, U2, U3 and U4 in modulator Mo.
  • the clock input t of the flip-flop F11 acted upon at its R input by the AND gate U13 is at the Q output, that is to say at the inverting output of the flip-flop, F6, which is also at an input of the AND gate U7 in Mo.
  • the non-inverting Q output of said flip-flop F6, is used to control one input each of the AND gates U3 and U11 of the modulator.
  • the non-inverting output Q of the first link F4 of the flip-flop chain is connected to an input of the AND gates U1, U5 and U9 of the modulator.
  • the Q output of the following flip-flop F5 is connected to one input of the AND gates U2, U6 and U10 of the modulator, while the connection of the outputs of the third D flip-flop stage F6 of the chain to the AND gates of the modulator Mo - as well as that of F8 and F9 - has already been specified.
  • the Q output of the D flip-flop F7 is at an input of the AND gate U4, and the Q output of the D flip-flop F11 clocked by the Q output F6 is at the clock input of the D- Flip-flops F12 and also connected to an input of the AND gate U8 of the modulator Mo and the Q output of the D-flip-flop F12 to an input of the AND gates U6, U7, U8 and U5 of the modulator.
  • modulator Mo consists of twelve AND gates U1 to U12, each of which has three inputs, one input each in the manner already described and evident from FIG. 4 either by one of the D- Flip-flops F4 to F12 or by one of the sound signal outputs I, II or III of the frequency divider circuit is controlled.
  • the output of the AND gates U1 to U12 forming the modulator Mo is via a resistor to to the node e, which, as already mentioned, is connected to the input of the differential amplifier V.
  • the switching point e thus forms the summation point, ie the mixer M.
  • the digital-to-analog converters DA1, DA2, DA3 are due to the group of resistors and or the group to respectively. to specified ben.
  • the resistances to are staggered and have z. B. the following values:
  • the resulting weighting of the resistors R * to R * 12 causes the DA conversion.
  • the three frequencies 660 Hz, 550 Hz and 440 Hz are derived by division from a mother oscillator 0, which oscillates at 13.2 kHz. One of the three frequencies is divided further, thereby gaining the time base for the decay process.
  • a four-bit D / A converter per tone generates the decay voltage, with which the three tones are switched on one after the other and weakened overlapping again.
  • the basic frequency is determined by an external RC element.
  • the output voltage is rectangular.
  • the harmonic content can be reduced by connecting a capacitor to connection 7 *. Volume control is also possible here with a potentiometer.
  • the circuit only draws current when it is active and switches off automatically after the tone sequence has subsided. The start is made by briefly switching on a voltage at input 1 * . If the trigger voltage is still or again after the tone sequence, the tone sequence is repeated. The triggering of the tone sequence is prevented if a trigger voltage at input 1 * is present for a shorter time than the duration of the dead time.
  • the external circuitry of the circuit according to the invention described above and preferably monolithically combined in a silicon wafer is done in the manner shown in FIG. 1.
  • the chip To containing the circuit is provided with the external connection pins 1 * - 7 * already defined above.
  • There the supply voltage is supplied by a DC voltage source UB, the pole of which supplies the first operating potential "+” or the activation switch Dt is connected to terminal 1 * and the pole of which supplies the reference potential "-" is connected to terminal 4 of the circuit To according to the invention.
  • the connection 3 leads via a capacitor C5 to the loudspeaker L and the other connection of the latter also to the reference potential.
  • connection 2 is connected via a capacitor C6 to the reference potential and also directly to the connection "+" of UB supplying the operating potential.
  • connection 6 * is connected to the reference potential via the series connection of the resistor R1 and the capacitor C1 and is also connected to the connection 5 via the resistor R1 of the timer. To improve the sound quality, it is advisable to connect terminal 7 to the reference potential via a capacitor C2.
  • the configuration of the circuit of the tone generator To shown in FIGS. 3, 4 and 5 leads to a temporal sequence of the tone sequence, as can be seen from the amplitude-time diagram according to FIG.
  • the first tone which for example, has given a frequency of 660 Hz (corresponding to the divider ratios and frequency of the mother oscillator 0 given in the description of FIG. 4) on the loudspeaker.
  • the second tone for example with a frequency of 550 Hz
  • the third tone comes with, for example, 440 Hz.
  • the first tone has subsided after 4.36 seconds, the second tone after 5.53 seconds and the third tone after 6.69 seconds.
  • the tone sequence is given again if the start signal St is still pending at the inputs 1 * and 2 * . It is understandable that the specified frequencies and expiry times are determined by the dimensioning of the circuit. However, it is not difficult to work with other tone sequences and other tone frequencies.
  • the superimposition of the simultaneously appearing amplitude values indicate the envelope curve and thus the temporal course of the sound image.
  • the tone sequence decays 6.69 sec after the onset of tone 1 of the tone sequence. A repetition is possible after 6.98 sec after the first triggering of the tone sequence.
  • the ratio of the maximum amplitudes M3: M2: M1 1: 0.89: 0.67.
  • the time scale for the oscillator frequency 13.2 kHz.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Mechanical Engineering (AREA)
  • Amplifiers (AREA)
  • Electrophonic Musical Instruments (AREA)
EP81108368A 1980-11-18 1981-10-15 Générateur de son Expired EP0052236B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE3043505 1980-11-18
DE19803043505 DE3043505A1 (de) 1980-11-18 1980-11-18 Tongenerator-halbleiterschaltung
DE19803050148 DE3050148A1 (de) 1980-11-18 1980-11-18 Tongenerator
DE3050148 1981-06-15

Publications (2)

Publication Number Publication Date
EP0052236A1 true EP0052236A1 (fr) 1982-05-26
EP0052236B1 EP0052236B1 (fr) 1985-05-02

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EP81108368A Expired EP0052236B1 (fr) 1980-11-18 1981-10-15 Générateur de son

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US (1) US4516113A (fr)
EP (1) EP0052236B1 (fr)
JP (1) JPS57114196A (fr)
DE (1) DE3170322D1 (fr)

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Publication number Priority date Publication date Assignee Title
US5633625A (en) * 1995-03-20 1997-05-27 Saturn Electronics & Engineering, Inc. Electronic chime module and method

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DE2149489B2 (de) * 1971-10-04 1974-01-03 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Klangrufeinrichtung
US4001816A (en) * 1975-01-21 1977-01-04 Matsushita Electric Works, Ltd. Electronic chime
JPS5429997A (en) * 1977-08-10 1979-03-06 Seiko Epson Corp Electronic tone generator
JPS54118202A (en) * 1978-03-06 1979-09-13 Matsushita Electric Works Ltd Chime
DE2823097A1 (de) * 1978-05-26 1979-11-29 Bachmann Wolfgang Elektronisch akustischer signalgeber
DE2829404A1 (de) * 1978-07-05 1980-01-17 Becker Autoradio Anordnung zur erzeugung einer periodischen signaltonfolge aus mindestens zwei frequenzen
DE2939401A1 (de) * 1978-09-28 1980-04-03 Rca Corp Elektronisches klangsignalgenerator
DE2850286A1 (de) * 1978-11-20 1980-06-19 Junghans Gmbh Geb Elektronische schlagwerksuhr

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JPS512798A (en) * 1974-06-28 1976-01-10 Hitachi Ltd Kayoseihoriimidono seizoho
US4073133A (en) * 1976-04-13 1978-02-14 General Time Corporation Electronic chime and strike system
JPS5393066A (en) * 1977-01-26 1978-08-15 Seiko Instr & Electronics Ltd Electronic watch with alarm
JPS5420714A (en) * 1977-07-15 1979-02-16 Matsushita Electric Works Ltd Audio circuit
JPS5429996A (en) * 1977-08-10 1979-03-06 Seiko Epson Corp Electronic tone generator
JPS6344872Y2 (fr) * 1980-06-03 1988-11-21

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Publication number Priority date Publication date Assignee Title
DE2149489B2 (de) * 1971-10-04 1974-01-03 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Klangrufeinrichtung
US4001816A (en) * 1975-01-21 1977-01-04 Matsushita Electric Works, Ltd. Electronic chime
DE2601922B2 (de) * 1975-01-21 1978-06-08 Matsushita Electric Industrial Co., Ltd. Elektronische Türglocke
JPS5429997A (en) * 1977-08-10 1979-03-06 Seiko Epson Corp Electronic tone generator
JPS54118202A (en) * 1978-03-06 1979-09-13 Matsushita Electric Works Ltd Chime
DE2823097A1 (de) * 1978-05-26 1979-11-29 Bachmann Wolfgang Elektronisch akustischer signalgeber
DE2829404A1 (de) * 1978-07-05 1980-01-17 Becker Autoradio Anordnung zur erzeugung einer periodischen signaltonfolge aus mindestens zwei frequenzen
DE2939401A1 (de) * 1978-09-28 1980-04-03 Rca Corp Elektronisches klangsignalgenerator
DE2850286A1 (de) * 1978-11-20 1980-06-19 Junghans Gmbh Geb Elektronische schlagwerksuhr

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Title
Funkschau, Band 52, Nr. 20 September 1980 Munchen K.D. REDECKER "Elektronische Turglocke" seiten 87 bis 90 *
PATENTS ABSTRACTS OF JAPAN Band 3, Nr. 139, 17. November 1979 seite 143E152 & JP - A - 54 - 118202 *
PATENTS ABSTRACTS OF JAPAN Band 3, Nr. 52, 7. Mai 1979 seite 4E108 & JP - A - 54 - 29997 *

Also Published As

Publication number Publication date
EP0052236B1 (fr) 1985-05-02
US4516113A (en) 1985-05-07
JPS57114196A (en) 1982-07-15
DE3170322D1 (en) 1985-06-05

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