EP0050549B1 - Unantastbare Schranke zum Schutz gegen das Eindringen - Google Patents

Unantastbare Schranke zum Schutz gegen das Eindringen Download PDF

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Publication number
EP0050549B1
EP0050549B1 EP81401559A EP81401559A EP0050549B1 EP 0050549 B1 EP0050549 B1 EP 0050549B1 EP 81401559 A EP81401559 A EP 81401559A EP 81401559 A EP81401559 A EP 81401559A EP 0050549 B1 EP0050549 B1 EP 0050549B1
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EP
European Patent Office
Prior art keywords
alarm
circuit
output
duration
pulses
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Expired
Application number
EP81401559A
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English (en)
French (fr)
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EP0050549A1 (de
Inventor
Pierre Durand
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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Publication of EP0050549A1 publication Critical patent/EP0050549A1/de
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00—Burglar, theft or intruder alarms
    • G08B13/18—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength
    • G08B13/181—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength using active radiation detection systems
    • G08B13/183—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength using active radiation detection systems by interruption of a radiation beam or barrier
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00—Burglar, theft or intruder alarms

Definitions

  • the present invention relates to a tamper-proof barrier against intrusion. This barrier is used to detect, at the edge of an area to be protected, any unwanted intrusion into this area, across this boundary.
  • protective barriers are used more and more often which are invisible to the intruder, but which make it possible to trigger an alarm when this intruder crosses the limit of the zone or room protected by the barrier.
  • Protective barriers are known which comprise means for transmitting signals modulated by pulses, in a predetermined code. These signals are mostly radio signals.
  • These barriers of known type also include means for receiving the modulated and coded signals transmitted as well as means for recognizing codes which are connected to the reception means and which provide a characteristic signal at output, each time the code is recognized. .
  • An alarm circuit is connected to these code recognition means; it allows an alarm to be triggered each time the characteristic signal is absent at the output of the code recognition means, that is to say each time the code is not recognized in the signals coming from program.
  • Various types of codes are used to prevent an intruder from knowing the code. Indeed, any individual having knowledge of the code could possibly replace the transmission means set up at the limit of the area to be protected, by transmission means "pirates emitting signals identical to those of the transmission means of the barrier, towards the reception means, which would allow it to cross the limit without setting off the alarm.
  • the object of the invention is to remedy these drawbacks and in particular to provide a tamper-proof protection barrier against intrusion which operates according to the same principle as barriers of known type, but in which the code emitted is very simple and is recognized by coincidence detection means which make it impossible to replace the barrier emission means with “pirate” emission means.
  • coincidence detection means which make it impossible to replace the barrier emission means with “pirate” emission means.
  • the use of this system of code recognition by detection of pulses by coincidence also makes it possible to simplify the logic circuits used.
  • the barrier of the invention overcomes the problems posed by background noise and parasitic ies in barriers that use radio signals, through the use of electromagnetic signals produced by a laser diode, infrared type for example.
  • the subject of the invention is a tamper-proof protection barrier against intrusion, comprising means for transmitting signals modulated and coded by pulses in a predetermined code, means for receiving the modulated and coded signals transmitted and means for recognizing the code predetermined in the received signals, these recognition means supplying an output with a characteristic signal each time the code is recognized, an alarm circuit, one input of which is connected to the output of the code recognition means, this circuit alarm providing an alarm signal in the absence of a characteristic signal, the code recognition means being constituted by a coincidence pulse detection system and the modulated and coded signals forming repetitive pulse trains, characterized in that that the coincidence pulse detection system comprises means for delaying, from the first pulse of each train, all the pulses ions which precede the last pulse of this train, so as to bring them into coincidence with the latter, and a logic gate circuit to control these coincidences, this logic gate circuit providing said characteristic signal on an output which constitutes the output of the system detection.
  • the transmission means consist of a laser diode controlled by a pulse code modulator and the reception means comprise a photodiode, one output of which is connected to an amplification and activation circuit. form, the output of this circuit constituting the output of the receiving means.
  • the transmission means consist of a generator of coded electromagnetic pulses and in that the reception means comprise a receiver, one output of which is connected to an amplification and shaping circuit, the output of this circuit constituting the output of the receiving means.
  • the circuit ' alarm comprises a monostable alarm triggering flip-flop, one input of which constitutes the input to this alarm circuit and one output of which is connected to an input of a voltage threshold detector circuit, the duration of the period conduction of the monostable trigger flip-flop being greater than the duration of the interval separating two trains of pulses while being less than the sum of the duration of two intervals.
  • the output of the detector circuit providing an alarm signal when the characteristic signal is absent, this absence causing the conduction of the monostable trigger rocker to stop.
  • the alarm circuit further comprises a monostable flip-flop for minimum alarm maintenance connected between the output of the trigger flip-flop and the input of the threshold detector circuit, the duration of the conduction period of this alarm holding toggle to set the minimum duration of the alarm signal.
  • the alarm circuit further comprises a logic gate with two inputs, these inputs being connected respectively to the outputs of the trigger flip-flop and of the minimum holding flip-flop, the output of this door being connected to the input of the threshold detector, so that the duration of the alarm signal is equal to the duration of the intrusion, when this intrusion has a duration greater than that of the conduction of the minimum alarm holding flip-flop.
  • the means for delaying the pulses comprise a counter, one input of which receives the pulses from each train and the outputs of which are respectively connected to the circuit inputs making it possible respectively to delay the pulses of each train, to bring them into coincidence with the last pulse of the train , another input of this counter being connected to a logic circuit for resetting to zero and for maintaining reset, this logic circuit being capable of causing and maintaining the reset of the counter, immediately after each coincidence detection, between two successive pulse trains.
  • the code recognition means 3 are constituted by a coincidence pulse detection system.
  • the emission means 1 are constituted by a laser diode 8 shown schematically in the figure; this laser diode is controlled in a known manner by a pulse code modulator 9.
  • the reception means 2 consist of a photodiode 10, an output 11 of which is connected in known manner to an amplification and shaping circuit 12.
  • the output 13 of this circuit constitutes the output of the receiving means.
  • the laser diode 8 is an infrared diode
  • the photodiode 10 is a photodiode sensitive to the wavelengths corresponding to the infrared.
  • the amplification and shaping means 12 are known in the state of the art and will not be described in detail.
  • These means preferably consist of a non-linear amplifier, operating in “all or nothing”, from a threshold level situated above the peak level of the total noise (at reception and at amplification). This threshold set by a comparator must be adjusted according to the maximum tolerable operating temperature of the barrier (50 ° C).
  • FIG. 2 shows schematically, but in more detail, the code recognition means 3 and the alarm circuit 5.
  • the code recognition means 3 are constituted by a detection system of coincidence pulses; this system receives on its input 14 the modulated and coded signals coming from the amplification and shaping means 12 (not shown in this figure). These modulated and coded signals are formed by repetitive pulse trains.
  • the coincidence pulse detection system comprises means 15 which make it possible, as will be seen later, to delay, from the first pulse of each train, all the pulses which precede the last pulse of this train, so as to bring them into coincidence with the latter.
  • This system also includes an AND type logic gate circuit, 16.17.18. which allows you to control coincidences.
  • This circuit provides on its output 4, in in case of coincidence of delayed pulses, the characteristic signal mentioned above, which is applied to input 6 of the alarm circuit 5.
  • the absence of this characteristic signal causes the appearance on the output 19 of the alarm circuit 5, of an alarm signal which triggers the alarm 7 (FIG. 1), not shown in this figure.
  • the alarm circuit 5 comprises a monostable flip-flop 20 for triggering an alarm, the input 6 of which constitutes the input of this alarm circuit; an output 21 of the flip-flop 20 is connected to an input 22 of a voltage detector circuit 23, the output 19 of which constitutes the output of the alarm circuit 5.
  • This threshold detector can be constituted, for example, by a relay.
  • the duration of the conduction period of the monostable flip-flop 20 is greater than the duration of the interval separating two trains of pulses (time interval between the first pulse of a train and the first pulse of the next train) received by the code recognition means 15, while being less than the sum of the duration of two intervals.
  • the output 19 of the voltage threshold detector circuit 23 provides an alarm signal when the signal characteristic of a coincidence is absent on the output of the code recognition circuit 3.
  • the alarm circuit 5 further comprises a monostable flip-flop for maintaining the minimum alarm 24, connected between the output 21 of the trigger flip-flop 20 and the input 22 of the threshold detector circuit 23. As will be seen below in detail, the duration of the conduction period of this alarm holding flip-flop makes it possible to set the duration of the minimum alarm signal applied to the threshold detector 23.
  • the alarm circuit 5 also comprises a logic gate 25 of the NAND type, with two inputs 26, 27 which are respectively connected to the outputs of the trigger latch 20 and of the minimum holding latch 24.
  • the output of this door is connected to the input 22 of the threshold detector 23 ; the combination of flip-flops 20 and 24 of logic gate 25 makes it possible to set the duration of the alarm when the intrusion is short-lived, or to maintain this alarm throughout the duration of the intrusion, if the latter has a duration greater than that of the conduction of the minimum holding lever 24.
  • the means 15 which make it possible to delay the pulses comprise a counter 28 whose input 14 receives the pulses from each train and whose outputs 29, 30, 31 are respectively connected to the inputs of circuits 32 which make it possible respectively to delay the pulses of each train, to bring them into coincidence with the last pulse of the train.
  • the first of these circuits makes it possible to delay the second pulse of each train; it is constituted for example by a first monostable rocker 33, capable of delaying the second pulse so as to bring it into coincidence with the last pulse of the train; this first monostable rocker is followed by a second monostable rocker 34 which makes it possible to shape this delayed pulse.
  • the second of these circuits which comprises for example an AND gate 35 followed by a first monostable rocker 36, makes it possible to offset the third pulse of the train, so as to bring it into coincidence with the last pulse of this train.
  • This delay is applied by a monostable rocker 36, the output of which is connected to the input of another monostable shaping rocker 37.
  • the delay circuits 32 include a derivative circuit C, R, on the fourth pulse, so as to limit its duration of effectiveness to approximately 200 ⁇ s, to thus form the last coincidence signal. This fourth pulse does not need to be delayed.
  • Another input 38 of the counter 28 is connected to a logic circuit for resetting and maintaining this reset; this circuit is constituted, for example, by the NAND gate 39 and by monostable flip-flops 40, 41.
  • this logic circuit makes it possible to cause and maintain the resetting of counter 28 immediately after each detection of coincidences.
  • the duration of the counting is fixed by the duration of the conduction period of the monostable flip-flop 41, while the flip-flop 40 makes it possible to maintain the reset of the counter immediately after each detection of coincidences, between two successive trains of pulses.
  • FIG. 3 is a timing diagram of the signals present at certain characteristic points of the barrier of the invention. The study of this chronogram allows to better understand the functioning of this barrier.
  • the diagram a in this figure represents the successive pulse trains T, supplied by the transmission means 1 of FIG. 1.
  • the transmitter supplies successive trains of pulses T, which respectively comprise four pulses, each pulse having a duration of 1 "and these pulses being separated by indicated time intervals It is also assumed that the pulse trains follow each other every 18 ms and that the time between the last pulse of a train and the first pulse of a next train is equal to 10.5 ms.
  • Diagram b represents the pulse trains received by the reception means 2. It is assumed that no intrusion has taken place and that no parasitic pulse has disturbed the barrier. This diagram represents the pulses at the output of photodiode 10; for example, they have a duration of 0.2 ⁇ s, which changes to 0.6 "at the output of the amplifier and before shaping.
  • Diagram c represents the pulses at the output of the amplification and shaping means 12. Each of these pulses has a duration of 50 pz for example.
  • the diagram d represents the output signal of the monostable flip-flop 41.
  • This signal makes it possible to fix the duration of the counting of the pulses and also makes it possible to determine, as will be seen hereinafter, the coincidences. In the absence of disturbances, this signal has a duration of 7.7 ms for example; it makes it possible to determine the coincidences in a 200 ⁇ s slot, having a delay of 7.5 ms with respect to the rise of the first pulse of the train.
  • the diagram e represents the output signal of the monostable flip-flop 40.
  • This signal which is at a high level in the absence of disturbances has a duration of 9.5 ms and makes it possible to maintain, during this duration, the reset to zero of the counter 28.
  • the monostable flip-flop 40 is triggered by the combination of the output signal of the flip-flop 41 and the output signal of the NAND gate 39.
  • the diagram f represents the output signal of the monostable flip-flop 33.
  • this signal has a duration of 5 ms corresponding to the delay applied to the second pulse of the train T.
  • Diagram g represents the second delayed pulse, after being shaped in the monostable flip-flop 34, this delayed pulse has a duration of 200 ⁇ s and it is applied to one of the inputs of AND gate 16 of the logic control circuit of coincidences.
  • the diagram h represents the output signal of the monostable flip-flop 36; this signal, which has a duration of 3.5 ms, represents the delay applied to the third pulse of train T.
  • Diagram i represents the third pulse of train T at the output of the monostable flip-flop 37, which realizes this pulse delayed by flip-flop 36.
  • This third shaped pulse has a duration of 200 ps; it is applied to the other input of door 16 of the coincidence control circuit 16, 17, 18.
  • Diagram i represents the output signal of the branch circuit R, C; this signal represents the derivative with respect to time, of the fourth and last pulse of the train; this pulse is not delayed but simply shaped, since the coincidences are determined from the rising edges of this last pulse.
  • the processing of this last pulse is carried out by a differentiating circuit, so as not to introduce parasitic delay on this pulse.
  • the output signal from this branch circuit is applied to one of the inputs of AND gate 17 of the coincidence control circuit; the other input of this AND gate receives the output signal from the monostable flip-flop 41, that is to say the signal shown in diagram d. If there is a coincidence between the different train pulses, delayed and processed in the manner described, the output signals from AND gates 16 and 17 are at a high level; these signals are applied to gate 18 of the coincidence control circuit which provides, in the event of coincidences, a characteristic signal with a duration of 200 (JLS. as shown in diagram k.
  • a characteristic signal such as that which is represented on the diagram k is supplied by the coincidence control circuit to the monostable flip-flop 20 of the alarm circuit 5;
  • this flip-flop which has a conduction period of 22 ms, greater than the duration of the interval between two trains of pulses, but less than the sum of the durations and two intervals, ie 18 ms ⁇ 22 ms ⁇ 2 x 18 ms, then presents an output whose signal remains constantly at a high level (logic level 1), while the output of the flip-flop 24 for maintaining the alarm also remains at a high level.
  • the logic signal is at a low level (level 0).
  • This low level signal is applied to relay 23 which is kept glued. If, on the other hand, an intrusion of very short duration occurs between the transmission and reception means, no coincidence signal is delivered to output 4 of the logic circuit for checking coincidences; the output 21 of the monostable trigger flip-flop 20 then goes from level 1 to level 0 and it follows that the output signal from the AND gate 25 goes to level 1, which takes off the relay 23 and triggers the alarm 7.
  • the output signal from the NAND gate 25 is maintained at a high level for a time which is fixed by the conduction duration of the minimum holding flip-flop 24; by way of example, this time is equal to 1 second and the output signal of this flip-flop, in this case, is represented on diagram 1.
  • the output signal of the alarm trigger flip-flop 21 remains at level 0 throughout the duration of this disturbance; it follows that the output signal from the NAND gate 25 remains at level 1 for the entire duration, although this gate has received at its input 26 a level 1 signal lasting 1 second.
  • the relay 23 receives for the entire duration of the disturbance, a level 1 signal which makes it possible to trigger the alarm for this entire duration.
  • any parasitic pulse which enters the sequence of pulses or any suppression of pulses from the code produces a shift in the counting time and disturbs the coincidences, which has the effect of triggering the alarm.
  • the monostable scales and the other components used in the barrier of the invention are not described in detail. Components such as flip-flops, diodes, photodiodes, etc., are known devices, available commercially.
  • the barrier of the invention can detect intrusions between two points close to 1000 meters.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Burglar Alarm Systems (AREA)

Claims (8)

1. Unantastbare Schranke zum Schutz gegen das Eindringen, mit Sendemitteln (1) für modulierte und mit einem vorbestimmten Code impulscodierte Signale, Empfangsmitteln (2) für die ausgesendeten, modulierten und codierten Signale und Mitteln (3), um den vorbestimmten Code in den empfangenen Signalen zu erkennen, wobei die Erkennungsmittel (3) an einem Ausgang (4) ein charakteristisches Signal jedesmal dann abgeben, wenn der Code erkannt ist, einem Alarmschaltkreis (5), dessen einer Eingang mit dem Ausgang (4) der Erkennungsmittel (3) für den Code verbunden ist, wobei der Alarmschaltkreis (5) ein Alarmsignal bei Abwesenheit des characteristischen Signals abgibt, die Erkennungsmittel (3) für den Code ein System zum Erfassen von Impulsen mittels Koinzidenz aufweist und die modulierten und codierten Signale wiederholbare Impulszüge (T) bilden, dadurch gekennzeichnet, daß das System (3) zum Erfassen von Impulsen mittels Koinzdenz Mittel (23) zum Verzögern aller derjenigen Impulse von dem ersten Impuls jeden Zuges an die dem letzten Impuls dieses Zuges vorausgehen derart, daß sie mit diesem letzten in Koinzidenz gebracht werden, und einen logischen Torschaltkreis (16, 17, 18) umfaßt, um diese Koinzidenzen zu überwachen, wobei der logische Torschaltkreis das charakteristische Signal an einem Ausgang (4) abgibt, welcher den Ausgang des Erfassungssystems (3) bildet.
2. Schranke nach Anspruch 1, dadurch gekennzeichnet, daß der Alarmschaltkreis (5) einen monostabilen Multivibrator (20) zum Alarmauslösen aufweist, dessen einer Eingang (6) den Eingang des Alarmschaltkreises (5) bildet und dessen einer Ausgang (21) mit einem Eingang (22) eines Schwellenspannungserfassungsschaltkreises (23) verbunden ist, daß die Zeitdauer während der der monostabile Multivibrator (20) leitet, länger als die zwei Impulszüge (T) trennende Intervallänge jedoch kürzer als die Summe von zwei Intervallängen ist, und daß der Ausgang (19) des Erfassungsschaltkreises (23) ein Alarmsignal abgibt, wenn das charakteristische Signal fehlt, wobei dieses Fehlen das Anhalten des Leitens des monostabilen Auslösemultivibrators (20) hervorruft.
3. Schranke nach Anspruch 2, dadurch gekennzeichnet, daß der Alarmschaltkreis (5) ferner einen monostabilen Muitivibrator (24) zum Aufrechterhalten eines minimalen Alarms aufweist, der zwischen dem Ausgang (21) des Auslösemultivibrators (20) und den Eingang (22) des Schwellenerfassungsschaltkreises (23) geschaltet ist, und daß die Leitungsperiode dieses Multivibrators zum Aufrechterhalten des Alarms (24) ermöglicht, die minimale Dauer des Alarmsignals festzulegen.
4. Schranke nach Anspruch 3, dadurch gekennzeichnet, daß der Alarmschaltkreis (5) ferner ein logisches Tor (25) mit zwei Eingängen umfaßt, die mit dem Ausgang des Auslösemultivibrators (20) bzw. des multivibrators (24) zum minimalen Aufrechterhalten verbunden sind, daß der Ausgang dieses Torres (25) mit dem Eingang (22) der Schwellenerfassungschaltung (23) derart verbunden ist, daß die Dauer des Alarmsignals gleich der Dauer des Eindringens ist, wenn dieses Eindringen länger dauert als das Leiten des Multivibrators (24) zum Aufrechterhalten eines minimalen Alarms.
5. Schranke nach Anspruch 1, dadurch gekennzeichnet, daß die Mittel zum Verzögern der Impulse einen Zähler (28) umfassen, dessen einer Eingang (14) die Impulse von jedem Zug (T) erhält und dessen Ausgänge (29, 30, 31) mit den entsprechenden Eingängen des Schaltkreises (32) verbunden sind, wodurch die Impulse jeden Zuges verzögerbar sind, um sie in Koinzidenz mit dem letzten Impuls des Zuges zu bringen, daß ein anderer Eingang (38) dieses Zählers (28) mit einem Logikkreis (39, 40, 41) zum Zurücksetzen auf Null und zum Aufrechterhalten des Zurücksetzens auf Null verbunden ist, wobei durch diesen Logikkreis das Zurücksetzen des Zählers auf Null unmittelbar nach jedem Erfassen von Koinzidenzen zwischen zwei aufeinanderfolgenden Impulszügen hervorrufbar und aufrechterhaltbar ist.
6. Schranke nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die Sendemittel (1) einen Diodenlaser (8) umfassen, der von einem Impulscodiermodulator (9) steuerbar ist, und daß die Empfangsmittel (2) eine Fotodiode (10) umfassen, deren einer Ausgang mit einem Verstärkungs- und Formungsschaltkreis (12) verbunden ist, wobei der Ausgang (13) dieses Kreises den Ausgang der Empfangsmittel (2) bildet.
7. Schranke nach Anspruch 6, dadurch gekennzeichnet, daß der Verstärkungs- und Formungsschaltkreis (12) einen nicht-linearen Verstärker mit einem « Alles-oder-Nichts »-Betrieb von einem Schwellenpegel an umfaßt, der über dem Spitzenpegel des gesamten Untergrundes beim Empfang und bei der Verstärkung liegt, wobei diese Schwelle durch eine Vergleichsschaltung festgelegt und in Abhängigkeit von der maximal zulässigen Temperatur des Betriebes der Schranke einstellbar ist.
8. Schranke nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß die Sendemittel (1) einen elektromagnetisch codierten lmpulsgenerator aufweisen.
EP81401559A 1980-10-13 1981-10-08 Unantastbare Schranke zum Schutz gegen das Eindringen Expired EP0050549B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8021825A FR2492136A1 (fr) 1980-10-13 1980-10-13 Barriere inviolable de protection contre les intrusions
FR8021825 1980-10-13

Publications (2)

Publication Number Publication Date
EP0050549A1 EP0050549A1 (de) 1982-04-28
EP0050549B1 true EP0050549B1 (de) 1985-07-17

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EP81401559A Expired EP0050549B1 (de) 1980-10-13 1981-10-08 Unantastbare Schranke zum Schutz gegen das Eindringen

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US (1) US4465998A (de)
EP (1) EP0050549B1 (de)
JP (1) JPS5797196A (de)
CA (1) CA1191227A (de)
DE (1) DE3171411D1 (de)
FR (1) FR2492136A1 (de)

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Publication number Priority date Publication date Assignee Title
GB2137388A (en) * 1983-03-30 1984-10-03 Bruce Stanley Gunton Improvements relating to a security system
US4583082A (en) * 1983-06-09 1986-04-15 Igt Optical door interlock
US4692752A (en) * 1984-08-27 1987-09-08 Sentrol, Inc. Moisture detector
US4633235A (en) * 1984-12-20 1986-12-30 Degennaro Charles S Optical cable security system with standby and automatic re-arming features
GR861382B (en) * 1985-11-13 1987-02-06 Pelta Elettronica S P A System for remote control of the antitheft protection devices of a property
US4829174A (en) * 1986-09-29 1989-05-09 General Motors Corporation Flexible tube optical intrusion detector
GB8829892D0 (en) * 1988-12-22 1989-09-13 Racal Guardall Scotland Radiation detection arrangements and methods
JPH032325U (de) * 1989-05-29 1991-01-10
US5144286A (en) * 1990-08-06 1992-09-01 Allen-Bradley Company, Inc. Photosensitive switch with circuit for indicating malfunction
JPH0561794U (ja) * 1992-01-27 1993-08-13 横河電機株式会社 液晶表示装置
GB2361058B (en) * 1999-03-17 2002-03-20 British Telecomm Detection system

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Publication number Priority date Publication date Assignee Title
US2984789A (en) * 1958-08-13 1961-05-16 Bell Telephone Labor Inc Pulse monitoring circuit
DE1566733C3 (de) * 1967-04-25 1975-08-28 Siemens Ag, 1000 Berlin Und 8000 Muenchen Durch Licht gesteuerte Anordnung zum Entriegeln und zur Überwachung eines Verschlusses
US3711846A (en) * 1971-02-08 1973-01-16 Holobeam Segment locating intrusion alarm system
US3852713A (en) * 1972-05-26 1974-12-03 V Roberts Alarm system having pulse pair coding
US3846794A (en) * 1973-03-15 1974-11-05 Baker Ind Inc Alarm retransmission system
FR2258639A1 (en) * 1974-01-18 1975-08-18 Thomson Csf Short distance target detection system - uses pulsed semiconductor laser transmission with correlation in receiver

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Publication number Publication date
EP0050549A1 (de) 1982-04-28
FR2492136A1 (fr) 1982-04-16
JPS6351317B2 (de) 1988-10-13
US4465998A (en) 1984-08-14
JPS5797196A (en) 1982-06-16
CA1191227A (en) 1985-07-30
DE3171411D1 (en) 1985-08-22
FR2492136B1 (de) 1983-12-09

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