EP0050549B1 - Inviolable barrier for the protection against intrusions - Google Patents

Inviolable barrier for the protection against intrusions Download PDF

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Publication number
EP0050549B1
EP0050549B1 EP81401559A EP81401559A EP0050549B1 EP 0050549 B1 EP0050549 B1 EP 0050549B1 EP 81401559 A EP81401559 A EP 81401559A EP 81401559 A EP81401559 A EP 81401559A EP 0050549 B1 EP0050549 B1 EP 0050549B1
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EP
European Patent Office
Prior art keywords
alarm
circuit
output
duration
pulses
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EP81401559A
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German (de)
French (fr)
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EP0050549A1 (en
Inventor
Pierre Durand
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00—Burglar, theft or intruder alarms
    • G08B13/18—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength
    • G08B13/181—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength using active radiation detection systems
    • G08B13/183—Actuation by interference with heat, light, or radiation of shorter wavelength; Actuation by intruding sources of heat, light, or radiation of shorter wavelength using active radiation detection systems by interruption of a radiation beam or barrier
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B13/00—Burglar, theft or intruder alarms

Definitions

  • the present invention relates to a tamper-proof barrier against intrusion. This barrier is used to detect, at the edge of an area to be protected, any unwanted intrusion into this area, across this boundary.
  • protective barriers are used more and more often which are invisible to the intruder, but which make it possible to trigger an alarm when this intruder crosses the limit of the zone or room protected by the barrier.
  • Protective barriers are known which comprise means for transmitting signals modulated by pulses, in a predetermined code. These signals are mostly radio signals.
  • These barriers of known type also include means for receiving the modulated and coded signals transmitted as well as means for recognizing codes which are connected to the reception means and which provide a characteristic signal at output, each time the code is recognized. .
  • An alarm circuit is connected to these code recognition means; it allows an alarm to be triggered each time the characteristic signal is absent at the output of the code recognition means, that is to say each time the code is not recognized in the signals coming from program.
  • Various types of codes are used to prevent an intruder from knowing the code. Indeed, any individual having knowledge of the code could possibly replace the transmission means set up at the limit of the area to be protected, by transmission means "pirates emitting signals identical to those of the transmission means of the barrier, towards the reception means, which would allow it to cross the limit without setting off the alarm.
  • the object of the invention is to remedy these drawbacks and in particular to provide a tamper-proof protection barrier against intrusion which operates according to the same principle as barriers of known type, but in which the code emitted is very simple and is recognized by coincidence detection means which make it impossible to replace the barrier emission means with “pirate” emission means.
  • coincidence detection means which make it impossible to replace the barrier emission means with “pirate” emission means.
  • the use of this system of code recognition by detection of pulses by coincidence also makes it possible to simplify the logic circuits used.
  • the barrier of the invention overcomes the problems posed by background noise and parasitic ies in barriers that use radio signals, through the use of electromagnetic signals produced by a laser diode, infrared type for example.
  • the subject of the invention is a tamper-proof protection barrier against intrusion, comprising means for transmitting signals modulated and coded by pulses in a predetermined code, means for receiving the modulated and coded signals transmitted and means for recognizing the code predetermined in the received signals, these recognition means supplying an output with a characteristic signal each time the code is recognized, an alarm circuit, one input of which is connected to the output of the code recognition means, this circuit alarm providing an alarm signal in the absence of a characteristic signal, the code recognition means being constituted by a coincidence pulse detection system and the modulated and coded signals forming repetitive pulse trains, characterized in that that the coincidence pulse detection system comprises means for delaying, from the first pulse of each train, all the pulses ions which precede the last pulse of this train, so as to bring them into coincidence with the latter, and a logic gate circuit to control these coincidences, this logic gate circuit providing said characteristic signal on an output which constitutes the output of the system detection.
  • the transmission means consist of a laser diode controlled by a pulse code modulator and the reception means comprise a photodiode, one output of which is connected to an amplification and activation circuit. form, the output of this circuit constituting the output of the receiving means.
  • the transmission means consist of a generator of coded electromagnetic pulses and in that the reception means comprise a receiver, one output of which is connected to an amplification and shaping circuit, the output of this circuit constituting the output of the receiving means.
  • the circuit ' alarm comprises a monostable alarm triggering flip-flop, one input of which constitutes the input to this alarm circuit and one output of which is connected to an input of a voltage threshold detector circuit, the duration of the period conduction of the monostable trigger flip-flop being greater than the duration of the interval separating two trains of pulses while being less than the sum of the duration of two intervals.
  • the output of the detector circuit providing an alarm signal when the characteristic signal is absent, this absence causing the conduction of the monostable trigger rocker to stop.
  • the alarm circuit further comprises a monostable flip-flop for minimum alarm maintenance connected between the output of the trigger flip-flop and the input of the threshold detector circuit, the duration of the conduction period of this alarm holding toggle to set the minimum duration of the alarm signal.
  • the alarm circuit further comprises a logic gate with two inputs, these inputs being connected respectively to the outputs of the trigger flip-flop and of the minimum holding flip-flop, the output of this door being connected to the input of the threshold detector, so that the duration of the alarm signal is equal to the duration of the intrusion, when this intrusion has a duration greater than that of the conduction of the minimum alarm holding flip-flop.
  • the means for delaying the pulses comprise a counter, one input of which receives the pulses from each train and the outputs of which are respectively connected to the circuit inputs making it possible respectively to delay the pulses of each train, to bring them into coincidence with the last pulse of the train , another input of this counter being connected to a logic circuit for resetting to zero and for maintaining reset, this logic circuit being capable of causing and maintaining the reset of the counter, immediately after each coincidence detection, between two successive pulse trains.
  • the code recognition means 3 are constituted by a coincidence pulse detection system.
  • the emission means 1 are constituted by a laser diode 8 shown schematically in the figure; this laser diode is controlled in a known manner by a pulse code modulator 9.
  • the reception means 2 consist of a photodiode 10, an output 11 of which is connected in known manner to an amplification and shaping circuit 12.
  • the output 13 of this circuit constitutes the output of the receiving means.
  • the laser diode 8 is an infrared diode
  • the photodiode 10 is a photodiode sensitive to the wavelengths corresponding to the infrared.
  • the amplification and shaping means 12 are known in the state of the art and will not be described in detail.
  • These means preferably consist of a non-linear amplifier, operating in “all or nothing”, from a threshold level situated above the peak level of the total noise (at reception and at amplification). This threshold set by a comparator must be adjusted according to the maximum tolerable operating temperature of the barrier (50 ° C).
  • FIG. 2 shows schematically, but in more detail, the code recognition means 3 and the alarm circuit 5.
  • the code recognition means 3 are constituted by a detection system of coincidence pulses; this system receives on its input 14 the modulated and coded signals coming from the amplification and shaping means 12 (not shown in this figure). These modulated and coded signals are formed by repetitive pulse trains.
  • the coincidence pulse detection system comprises means 15 which make it possible, as will be seen later, to delay, from the first pulse of each train, all the pulses which precede the last pulse of this train, so as to bring them into coincidence with the latter.
  • This system also includes an AND type logic gate circuit, 16.17.18. which allows you to control coincidences.
  • This circuit provides on its output 4, in in case of coincidence of delayed pulses, the characteristic signal mentioned above, which is applied to input 6 of the alarm circuit 5.
  • the absence of this characteristic signal causes the appearance on the output 19 of the alarm circuit 5, of an alarm signal which triggers the alarm 7 (FIG. 1), not shown in this figure.
  • the alarm circuit 5 comprises a monostable flip-flop 20 for triggering an alarm, the input 6 of which constitutes the input of this alarm circuit; an output 21 of the flip-flop 20 is connected to an input 22 of a voltage detector circuit 23, the output 19 of which constitutes the output of the alarm circuit 5.
  • This threshold detector can be constituted, for example, by a relay.
  • the duration of the conduction period of the monostable flip-flop 20 is greater than the duration of the interval separating two trains of pulses (time interval between the first pulse of a train and the first pulse of the next train) received by the code recognition means 15, while being less than the sum of the duration of two intervals.
  • the output 19 of the voltage threshold detector circuit 23 provides an alarm signal when the signal characteristic of a coincidence is absent on the output of the code recognition circuit 3.
  • the alarm circuit 5 further comprises a monostable flip-flop for maintaining the minimum alarm 24, connected between the output 21 of the trigger flip-flop 20 and the input 22 of the threshold detector circuit 23. As will be seen below in detail, the duration of the conduction period of this alarm holding flip-flop makes it possible to set the duration of the minimum alarm signal applied to the threshold detector 23.
  • the alarm circuit 5 also comprises a logic gate 25 of the NAND type, with two inputs 26, 27 which are respectively connected to the outputs of the trigger latch 20 and of the minimum holding latch 24.
  • the output of this door is connected to the input 22 of the threshold detector 23 ; the combination of flip-flops 20 and 24 of logic gate 25 makes it possible to set the duration of the alarm when the intrusion is short-lived, or to maintain this alarm throughout the duration of the intrusion, if the latter has a duration greater than that of the conduction of the minimum holding lever 24.
  • the means 15 which make it possible to delay the pulses comprise a counter 28 whose input 14 receives the pulses from each train and whose outputs 29, 30, 31 are respectively connected to the inputs of circuits 32 which make it possible respectively to delay the pulses of each train, to bring them into coincidence with the last pulse of the train.
  • the first of these circuits makes it possible to delay the second pulse of each train; it is constituted for example by a first monostable rocker 33, capable of delaying the second pulse so as to bring it into coincidence with the last pulse of the train; this first monostable rocker is followed by a second monostable rocker 34 which makes it possible to shape this delayed pulse.
  • the second of these circuits which comprises for example an AND gate 35 followed by a first monostable rocker 36, makes it possible to offset the third pulse of the train, so as to bring it into coincidence with the last pulse of this train.
  • This delay is applied by a monostable rocker 36, the output of which is connected to the input of another monostable shaping rocker 37.
  • the delay circuits 32 include a derivative circuit C, R, on the fourth pulse, so as to limit its duration of effectiveness to approximately 200 ⁇ s, to thus form the last coincidence signal. This fourth pulse does not need to be delayed.
  • Another input 38 of the counter 28 is connected to a logic circuit for resetting and maintaining this reset; this circuit is constituted, for example, by the NAND gate 39 and by monostable flip-flops 40, 41.
  • this logic circuit makes it possible to cause and maintain the resetting of counter 28 immediately after each detection of coincidences.
  • the duration of the counting is fixed by the duration of the conduction period of the monostable flip-flop 41, while the flip-flop 40 makes it possible to maintain the reset of the counter immediately after each detection of coincidences, between two successive trains of pulses.
  • FIG. 3 is a timing diagram of the signals present at certain characteristic points of the barrier of the invention. The study of this chronogram allows to better understand the functioning of this barrier.
  • the diagram a in this figure represents the successive pulse trains T, supplied by the transmission means 1 of FIG. 1.
  • the transmitter supplies successive trains of pulses T, which respectively comprise four pulses, each pulse having a duration of 1 "and these pulses being separated by indicated time intervals It is also assumed that the pulse trains follow each other every 18 ms and that the time between the last pulse of a train and the first pulse of a next train is equal to 10.5 ms.
  • Diagram b represents the pulse trains received by the reception means 2. It is assumed that no intrusion has taken place and that no parasitic pulse has disturbed the barrier. This diagram represents the pulses at the output of photodiode 10; for example, they have a duration of 0.2 ⁇ s, which changes to 0.6 "at the output of the amplifier and before shaping.
  • Diagram c represents the pulses at the output of the amplification and shaping means 12. Each of these pulses has a duration of 50 pz for example.
  • the diagram d represents the output signal of the monostable flip-flop 41.
  • This signal makes it possible to fix the duration of the counting of the pulses and also makes it possible to determine, as will be seen hereinafter, the coincidences. In the absence of disturbances, this signal has a duration of 7.7 ms for example; it makes it possible to determine the coincidences in a 200 ⁇ s slot, having a delay of 7.5 ms with respect to the rise of the first pulse of the train.
  • the diagram e represents the output signal of the monostable flip-flop 40.
  • This signal which is at a high level in the absence of disturbances has a duration of 9.5 ms and makes it possible to maintain, during this duration, the reset to zero of the counter 28.
  • the monostable flip-flop 40 is triggered by the combination of the output signal of the flip-flop 41 and the output signal of the NAND gate 39.
  • the diagram f represents the output signal of the monostable flip-flop 33.
  • this signal has a duration of 5 ms corresponding to the delay applied to the second pulse of the train T.
  • Diagram g represents the second delayed pulse, after being shaped in the monostable flip-flop 34, this delayed pulse has a duration of 200 ⁇ s and it is applied to one of the inputs of AND gate 16 of the logic control circuit of coincidences.
  • the diagram h represents the output signal of the monostable flip-flop 36; this signal, which has a duration of 3.5 ms, represents the delay applied to the third pulse of train T.
  • Diagram i represents the third pulse of train T at the output of the monostable flip-flop 37, which realizes this pulse delayed by flip-flop 36.
  • This third shaped pulse has a duration of 200 ps; it is applied to the other input of door 16 of the coincidence control circuit 16, 17, 18.
  • Diagram i represents the output signal of the branch circuit R, C; this signal represents the derivative with respect to time, of the fourth and last pulse of the train; this pulse is not delayed but simply shaped, since the coincidences are determined from the rising edges of this last pulse.
  • the processing of this last pulse is carried out by a differentiating circuit, so as not to introduce parasitic delay on this pulse.
  • the output signal from this branch circuit is applied to one of the inputs of AND gate 17 of the coincidence control circuit; the other input of this AND gate receives the output signal from the monostable flip-flop 41, that is to say the signal shown in diagram d. If there is a coincidence between the different train pulses, delayed and processed in the manner described, the output signals from AND gates 16 and 17 are at a high level; these signals are applied to gate 18 of the coincidence control circuit which provides, in the event of coincidences, a characteristic signal with a duration of 200 (JLS. as shown in diagram k.
  • a characteristic signal such as that which is represented on the diagram k is supplied by the coincidence control circuit to the monostable flip-flop 20 of the alarm circuit 5;
  • this flip-flop which has a conduction period of 22 ms, greater than the duration of the interval between two trains of pulses, but less than the sum of the durations and two intervals, ie 18 ms ⁇ 22 ms ⁇ 2 x 18 ms, then presents an output whose signal remains constantly at a high level (logic level 1), while the output of the flip-flop 24 for maintaining the alarm also remains at a high level.
  • the logic signal is at a low level (level 0).
  • This low level signal is applied to relay 23 which is kept glued. If, on the other hand, an intrusion of very short duration occurs between the transmission and reception means, no coincidence signal is delivered to output 4 of the logic circuit for checking coincidences; the output 21 of the monostable trigger flip-flop 20 then goes from level 1 to level 0 and it follows that the output signal from the AND gate 25 goes to level 1, which takes off the relay 23 and triggers the alarm 7.
  • the output signal from the NAND gate 25 is maintained at a high level for a time which is fixed by the conduction duration of the minimum holding flip-flop 24; by way of example, this time is equal to 1 second and the output signal of this flip-flop, in this case, is represented on diagram 1.
  • the output signal of the alarm trigger flip-flop 21 remains at level 0 throughout the duration of this disturbance; it follows that the output signal from the NAND gate 25 remains at level 1 for the entire duration, although this gate has received at its input 26 a level 1 signal lasting 1 second.
  • the relay 23 receives for the entire duration of the disturbance, a level 1 signal which makes it possible to trigger the alarm for this entire duration.
  • any parasitic pulse which enters the sequence of pulses or any suppression of pulses from the code produces a shift in the counting time and disturbs the coincidences, which has the effect of triggering the alarm.
  • the monostable scales and the other components used in the barrier of the invention are not described in detail. Components such as flip-flops, diodes, photodiodes, etc., are known devices, available commercially.
  • the barrier of the invention can detect intrusions between two points close to 1000 meters.

Description

. La présente invention concerne une barrière inviolable de protection contre les intrusions. Cette barrière est utilisée pour détecter, à la limite d'une zone à protéger, toute intrusion indésirable dans cette zone, à travers cette limite.. The present invention relates to a tamper-proof barrier against intrusion. This barrier is used to detect, at the edge of an area to be protected, any unwanted intrusion into this area, across this boundary.

Pour des raisons de sécurité, afin de protéger des locaux ou des zones, contre des intrusions indésirables, on utilise de plus en plus souvent des barrières de protection qui sont invisibles de l'intrus, mais qui permettent de déclencher une alarme lorsque cet intrus traverse la limite de la zone ou du local protégé par la barrière. On connaît des barrières de protection qui comprennent des moyens d'émissions de signaux modulés par impulsions, dans un code prédéterminé. Ces signaux sont la plupart du temps des signaux radioélectriques. Ces barrières de type connu, comprennent également des moyens de réception des signaux modulés et codés émis ainsi que des moyens de reconnaissance de codes qui sont reliés aux moyens de réception et qui fournissent en sortie un signai caractéristique, à chaque fois que le code est reconnu. Un circuit d'alarme est relié à ces moyens de reconnaissance de code ; il permet de déclencher une alarme chaque fois que le signal caractéristique est absent à la sortie des moyens de reconnaissance de code, c'est-à-dire à chaque fois que le code n'est pas reconnu dans les signaux provenant de moyens d'émission. Divers types de codes, plus ou moins compliqués, sont utilisés afin d'éviter qu'un intrus ne puisse avoir connaissance du code. En effet, tout individu ayant connaissance du code pourrait éventuellement remplacer les moyens d'émission mis en place à la limite de la zone à protéger, par des moyens d'émission « pirates émettant des signaux identiques à ceux des moyens d'émission de la barrière, en direction des moyens de réception, ce qui lui permettrait ainsi de traverser la limite sans déclencher l'alarme. De plus, les barrières existantes qui fonctionnent à partir de signaux radioélectriques sont fortement soumises aux impulsions parasites et aux bruits de fond ; ces impulsions parasites et ces bruits de fond peuvent déclencher des alarmes intempestives, ce qui a pour inconvénient de rendre de telles barrières peu fiables. Enfin, dans ces barrières connues, la complication des codes utilisés entraîne bien entendu une complication des circuits logiques de codage à l'émission et des circuits logiques de décodage à la réception. Des barrières de ce type sont décrites dans le document DE-A 1 566 733 ainsi que dans le document FR-A-2 258 639.For security reasons, in order to protect premises or zones against unwanted intrusions, protective barriers are used more and more often which are invisible to the intruder, but which make it possible to trigger an alarm when this intruder crosses the limit of the zone or room protected by the barrier. Protective barriers are known which comprise means for transmitting signals modulated by pulses, in a predetermined code. These signals are mostly radio signals. These barriers of known type also include means for receiving the modulated and coded signals transmitted as well as means for recognizing codes which are connected to the reception means and which provide a characteristic signal at output, each time the code is recognized. . An alarm circuit is connected to these code recognition means; it allows an alarm to be triggered each time the characteristic signal is absent at the output of the code recognition means, that is to say each time the code is not recognized in the signals coming from program. Various types of codes, more or less complicated, are used to prevent an intruder from knowing the code. Indeed, any individual having knowledge of the code could possibly replace the transmission means set up at the limit of the area to be protected, by transmission means "pirates emitting signals identical to those of the transmission means of the barrier, towards the reception means, which would allow it to cross the limit without setting off the alarm. In addition, existing barriers that operate from radio signals are highly subject to parasitic pulses and background noise; these parasitic pulses and these background noises can trigger nuisance alarms, which has the disadvantage of making such barriers unreliable. Finally, in these known barriers, the complication of the codes used naturally leads to a complication of the logic circuits for coding on transmission and of the logic circuits for decoding on reception. Barriers of this type are described in document DE-A 1 566 733 as well as in document FR-A-2 258 639.

L'invention a pour but de remédier à ces inconvénients et notamment de réaliser une barrière inviolable de protection contre les intrusions qui fonctionne selon le même principe que les barrières de type connu, mais dans laquelle le code émis est très simple et est reconnu grâce à des moyens de détection par coïncidences qui rendent impossible le remplacement des moyens d'émission de la barrière par des moyens d'émissions « pirates •. L'utilisation de ce système de reconnaissance de codes par détection d'impulsions par coïncidences, permet également de simplifier les circuits logiques utilisés. Enfin, la barrière de l'invention permet de s'affranchir des problèmes posés par les bruits de fond et ies parasites dans les barrières qui utilisent des signaux radioélectriques, grâce à l'utilisation de signaux électromagnétiques produits par une diode laser, de type infrarouge par exemple. Ces problèmes sont aussi résolus grâce à l'utilisation d'un amplificateur non linéaire, fonctionnant en « tout ou rien • , à partir d'un niveau de seuil situé au-dessus du niveau crête du bruit total (à la réception et à l'amplification). Ce seuil fixé par un comparateur doit être ajusté en fonction de ia température maximum tolérable de fonctionnement de la barrière (50 °C).The object of the invention is to remedy these drawbacks and in particular to provide a tamper-proof protection barrier against intrusion which operates according to the same principle as barriers of known type, but in which the code emitted is very simple and is recognized by coincidence detection means which make it impossible to replace the barrier emission means with “pirate” emission means. The use of this system of code recognition by detection of pulses by coincidence, also makes it possible to simplify the logic circuits used. Finally, the barrier of the invention overcomes the problems posed by background noise and parasitic ies in barriers that use radio signals, through the use of electromagnetic signals produced by a laser diode, infrared type for example. These problems are also resolved by the use of a non-linear amplifier, operating in “all or nothing”, from a threshold level situated above the peak level of total noise (at reception and at reception). 'amplification). This threshold set by a comparator must be adjusted according to the maximum tolerable operating temperature of the barrier (50 ° C).

L'invention a pour objet une barrière inviolable de protection contre les intrusions, comprenant des moyens d'émission de signaux modulés et codés par impulsions dans un code prédéterminé, des moyens de réception des signaux modulés et codés émis et des moyens pour reconnaître le code prédéterminé dans les signaux reçus, ces moyens de reconnaissance fournissant sur une sortie un signal caractéristique à chaque fois que le code est reconnu, un circuit d'alarme dont une entrée est reliée à la sortie des moyens de reconnaissance de code, ce circuit d'alarme fournissant un signal d'alarme en l'absence de signal caractéristique, les moyens de reconnaissance de code étant constitués par un système de détection d'impulsions par coïncidences et les signaux modulés et codés formant des trains d'impulsions répétitifs, caractérisée en ce que le système de détection d'impulsions par coïncidences comprend des moyens pour retarder, à partir de la première impulsion de chaque train, toutes les impulsions qui précèdent la dernière impulsion de ce train, de manière à les amener en coïncidence avec cette dernière, et un circuit à portes logiques pour contrôler ces coïncidences, ce circuit à portes logiques fournissant ledit signal caractéristique sur une sortie qui constitue la sortie du système de détection.The subject of the invention is a tamper-proof protection barrier against intrusion, comprising means for transmitting signals modulated and coded by pulses in a predetermined code, means for receiving the modulated and coded signals transmitted and means for recognizing the code predetermined in the received signals, these recognition means supplying an output with a characteristic signal each time the code is recognized, an alarm circuit, one input of which is connected to the output of the code recognition means, this circuit alarm providing an alarm signal in the absence of a characteristic signal, the code recognition means being constituted by a coincidence pulse detection system and the modulated and coded signals forming repetitive pulse trains, characterized in that that the coincidence pulse detection system comprises means for delaying, from the first pulse of each train, all the pulses ions which precede the last pulse of this train, so as to bring them into coincidence with the latter, and a logic gate circuit to control these coincidences, this logic gate circuit providing said characteristic signal on an output which constitutes the output of the system detection.

Selon une autre caractéristique de l'invention, les moyens d'émission sont constitués par une diode laser commandée par un modulateur à impulsions codées et les moyens de réception comprennent une photodiode dont une sortie est reliée à un circuit d'amplification et de mise en forme, la sortie de ce circuit constituant la sortie des moyens de réception.According to another characteristic of the invention, the transmission means consist of a laser diode controlled by a pulse code modulator and the reception means comprise a photodiode, one output of which is connected to an amplification and activation circuit. form, the output of this circuit constituting the output of the receiving means.

Selon une autre caractéristique, les moyens d'émission sont constitués par un générateur d'impulsions électromagnétiques codées et en ce que les moyens de réception comprennent un récepteur dont une sortie est reliée à un circuit d'amplification et de mise en forme, la sortie de ce circuit constituant la sortie des moyens de réception.According to another characteristic, the transmission means consist of a generator of coded electromagnetic pulses and in that the reception means comprise a receiver, one output of which is connected to an amplification and shaping circuit, the output of this circuit constituting the output of the receiving means.

Selon une autre caractéristique, le circuit ' d'alarme comprend une bascule monostable de déclenchement d'alarme, dont une entrée constitue l'entrée de ce circuit d'alarme et dont une sortie est reliée à une entrée d'un circuit détecteur de seuil de tension, la durée de la période de conduction de la bascule monostable de déclenchement étant supérieure à la durée de l'intervalle séparant deux trains d'impulsions tout en étant inférieure à la somme de la durée de deux intervalles. La sortie du circuit détecteur fournissant un signal d'alarme lorsque le signal caractéristique est absent, cette absence provoquant l'arrêt de la conduction de la bascule monostable de déclenchement.According to another characteristic, the circuit ' alarm comprises a monostable alarm triggering flip-flop, one input of which constitutes the input to this alarm circuit and one output of which is connected to an input of a voltage threshold detector circuit, the duration of the period conduction of the monostable trigger flip-flop being greater than the duration of the interval separating two trains of pulses while being less than the sum of the duration of two intervals. The output of the detector circuit providing an alarm signal when the characteristic signal is absent, this absence causing the conduction of the monostable trigger rocker to stop.

Selon une autre caractéristique, le circuit d'alarme comprend en outre une bascule monostable de maintien d'alarme minimum connectée entre la sortie de la bascule de déclenchement et l'entrée du circuit détecteur de seuil, la durée de la période de conduction de cette bascule de maintien d'alarme permettant de fixer la durée minimum du signal d'alarme.According to another characteristic, the alarm circuit further comprises a monostable flip-flop for minimum alarm maintenance connected between the output of the trigger flip-flop and the input of the threshold detector circuit, the duration of the conduction period of this alarm holding toggle to set the minimum duration of the alarm signal.

Selon une autre caractéristique, le circuit d'alarme comprend en outre une porte logique à deux entrées, ces entrées étant reliées respectivement aux sorties de la bascule de déclenchement et de la bascule de maintien minimum, la sortie de cette porte étant reliée à l'entrée du détecteur de seuil, de sorte que la durée du signal d'alarme est égale à la durée de l'intrusion, lorsque cette intrusion présente une durée supérieure à celle de la conduction de la bascule de maintien d'alarme minimum.According to another characteristic, the alarm circuit further comprises a logic gate with two inputs, these inputs being connected respectively to the outputs of the trigger flip-flop and of the minimum holding flip-flop, the output of this door being connected to the input of the threshold detector, so that the duration of the alarm signal is equal to the duration of the intrusion, when this intrusion has a duration greater than that of the conduction of the minimum alarm holding flip-flop.

Selon une autre caractéristique; les moyens pour retarder les impulsions comprennent un compteur dont une entrée reçoit les impulsions de chaque train et dont les sorties sont respectivement reliées aux entrées de circuits permettant de retarder respectivement les impulsions de chaque train, pour les amener en coïncidence avec la dernière impulsion du train, une autre entrée de ce compteur étant reliée à un circuit logique de remise à zéro et de maintien de remise à zéro, ce circuit logique étant apte à provoquer et à maintenir la remise à zéro du compteur, immédiatement après chaque détection de coïncidence, entre deux trains successifs d'impulsions.According to another characteristic; the means for delaying the pulses comprise a counter, one input of which receives the pulses from each train and the outputs of which are respectively connected to the circuit inputs making it possible respectively to delay the pulses of each train, to bring them into coincidence with the last pulse of the train , another input of this counter being connected to a logic circuit for resetting to zero and for maintaining reset, this logic circuit being capable of causing and maintaining the reset of the counter, immediately after each coincidence detection, between two successive pulse trains.

D'autres caractéristiques et avantages de l'invention ressortiront mieux de la description qui va suivre, donnée en référence aux dessins annexés dans lesquels :

  • la figure 1 représente schématiquement une barrière conforme à l'invention ;
  • la figure 2 représente schématiquement mais de manière plus détaillée les moyens de reconnaissance de code et le circuit d'alarme de la barrière de l'invention ;
  • la figure 3 est un chronogramme des différents signaux qui apparaissent en des points caractéristiques des moyens de réception de la barrière de l'invention.
  • La figure 1 représente schématiquement et par blocs, une barrière inviolable de protection contre les intrusions, conforme à l'invention. Cette barrière comprend des moyens d'émission 1 de signaux modulés et codés par impulsions, dans un code prédéterminé, et, des moyens de réception 2 des signaux modulés et codés émis. Des moyens 3 qui sont reliés aux moyens de réception 2 permettent de reconnaître le code prédéterminé dans les signaux reçus et fournissent sur une sortie 4 un signal caractéristique à chaque fois que le code d'émission est reconnu. Un circuit d'alarme 5, dont une entrée 6 est reliée à la sortie 4 des moyens de reconnaissance 3, fournit un signal d'alarme, en l'absence de signal caractéristique sur son entrée 6. On a représenté schématiquement en 7 une alarme sonore, mais il est bien évident que cette alarme pourrait être visuelle par exemple.
Other characteristics and advantages of the invention will emerge more clearly from the description which follows, given with reference to the appended drawings in which:
  • Figure 1 schematically shows a barrier according to the invention;
  • Figure 2 shows schematically but in more detail the code recognition means and the alarm circuit of the barrier of the invention;
  • FIG. 3 is a timing diagram of the various signals which appear at characteristic points of the means for receiving the barrier of the invention.
  • Figure 1 shows schematically and in blocks, a tamper-proof barrier against intrusion, according to the invention. This barrier comprises means 1 for transmitting pulse modulated and coded signals in a predetermined code, and means 2 for receiving modulated and coded signals transmitted. Means 3 which are connected to the reception means 2 make it possible to recognize the predetermined code in the received signals and provide on an output 4 a characteristic signal each time the transmission code is recognized. An alarm circuit 5, an input 6 of which is connected to the output 4 of the recognition means 3, provides an alarm signal, in the absence of a characteristic signal on its input 6. An alarm is represented diagrammatically at 7 audible, but it is obvious that this alarm could be visual for example.

Comme on le verra plus loin en détail, les moyens 3 de reconnaissance de code sont constitués par un système de détection d'impulsions par coïncidences. Dans l'invention, les moyens d'émission 1 sont constitués par une diode laser 8 représentée schématique sur la figure ; cette diode laser est commandée de manière connue par un modulateur à impulsions codées 9. Les moyens de réception 2 sont constitués par une photodiode 10 dont une sortie 11 est reliée de manière connue à un circuit d'amplification et de mise en forme 12. La sortie 13 de ce circuit constitue la sortie des moyens de réception. De préférence, la diode laser 8 est une diode infrarouge, tandis que la photodiode 10 est une photodiode sensible aux longueurs d'ondes correspondant à l'infrarouge. Les moyens d'amplification et de mise en forme 12 sont connus dans l'état de la technique et ne seront pas décrits en détail. Ces moyens sont constitués de préférence pour un amplificateur non linéaire, fonctionnant en « tout ou rien •, à partir d'un niveau de seuil situé au-dessus du niveau crête du bruit total (à la réception et à l'amplification). Ce seuil fixé par un comparateur doit être ajusté en fonction de la température maximum tolérable de fonctionnement de la barrière (50 °C).As will be seen in detail below, the code recognition means 3 are constituted by a coincidence pulse detection system. In the invention, the emission means 1 are constituted by a laser diode 8 shown schematically in the figure; this laser diode is controlled in a known manner by a pulse code modulator 9. The reception means 2 consist of a photodiode 10, an output 11 of which is connected in known manner to an amplification and shaping circuit 12. The output 13 of this circuit constitutes the output of the receiving means. Preferably, the laser diode 8 is an infrared diode, while the photodiode 10 is a photodiode sensitive to the wavelengths corresponding to the infrared. The amplification and shaping means 12 are known in the state of the art and will not be described in detail. These means preferably consist of a non-linear amplifier, operating in “all or nothing”, from a threshold level situated above the peak level of the total noise (at reception and at amplification). This threshold set by a comparator must be adjusted according to the maximum tolerable operating temperature of the barrier (50 ° C).

La figure 2 représente schématiquement, mais de manière plus détaillée, les moyens de reconnaissance de code 3 et le circuit d'alarme 5. Comme on l'a mentionné plus haut, les moyens 3 de reconnaissance de code sont constitués par un système de détection d'impulsions par coïncidences ; ce système reçoit sur son entrée 14 les signaux modulés et codés en provenance des moyens d'amplification et de mise en forme 12 (non représentés sur cette figure). Ces signaux modulés et codés sont formés par des trains d'impulsions répétitifs.Figure 2 shows schematically, but in more detail, the code recognition means 3 and the alarm circuit 5. As mentioned above, the code recognition means 3 are constituted by a detection system of coincidence pulses; this system receives on its input 14 the modulated and coded signals coming from the amplification and shaping means 12 (not shown in this figure). These modulated and coded signals are formed by repetitive pulse trains.

Le système de détection d'impulsions par coïncidences comprend des moyens 15 qui permettent, comme on le verra par la suite, de retarder, à partir de la première impulsion de chaque train, toutes les impulsions qui précèdent la dernière impulsion de ce train, de manière à les amener en coïncidences avec cette dernière. Ce système comprend également un circuit à portes logiques de type ET, 16.17,18. qui permet de contrôler les coïncidences. Ce circuit fournit sur sa sortie 4, en cas de coïncidences des impulsions retardées, le signal caractéristique mentionné plus haut, qui est appliqué à l'entrée 6 du circuit d'alarme 5. Comme on le verra plus loin en détail, l'absence de ce signal caractéristique entraîne l'apparition sur la sortie 19 du circuit d'alarme 5, d'un signal d'alarme qui déclenche l'alarme 7 (figure 1), non représentée sur cette figure.The coincidence pulse detection system comprises means 15 which make it possible, as will be seen later, to delay, from the first pulse of each train, all the pulses which precede the last pulse of this train, so as to bring them into coincidence with the latter. This system also includes an AND type logic gate circuit, 16.17.18. which allows you to control coincidences. This circuit provides on its output 4, in in case of coincidence of delayed pulses, the characteristic signal mentioned above, which is applied to input 6 of the alarm circuit 5. As will be seen below in detail, the absence of this characteristic signal causes the appearance on the output 19 of the alarm circuit 5, of an alarm signal which triggers the alarm 7 (FIG. 1), not shown in this figure.

Le circuit d'alarme 5 comprend une bascule monostable 20 de déclenchement d'alarme dont l'entrée 6 constitue l'entrée de ce circuit d'alarme ; une sortie 21 de la bascule 20 est reliée à une entrée 22 d'un circuit détecteur de tension 23, dont la sortie 19 constitue la sortie du circuit d'alarme 5. Ce détecteur de seuil peut être constitué par exemple, par un relais. La durée de la période de conduction de la bascule monostable 20 est supérieure à la durée de l'intervalle séparant deux trains d'impulsions (intervalle de temps entre la première impulsion d'un train et la première impulsion du train suivant) reçu par les moyens de reconnaissance de code 15, tout en étant inférieure à la somme de la durée de deux intervalles. La sortie 19 du circuit détecteur de seuil de tension 23 fournit un signal d'alarme lorsque le signal caractéristique d'une coïncidence est absent sur la sortie du circuit de reconnaissance de code 3.The alarm circuit 5 comprises a monostable flip-flop 20 for triggering an alarm, the input 6 of which constitutes the input of this alarm circuit; an output 21 of the flip-flop 20 is connected to an input 22 of a voltage detector circuit 23, the output 19 of which constitutes the output of the alarm circuit 5. This threshold detector can be constituted, for example, by a relay. The duration of the conduction period of the monostable flip-flop 20 is greater than the duration of the interval separating two trains of pulses (time interval between the first pulse of a train and the first pulse of the next train) received by the code recognition means 15, while being less than the sum of the duration of two intervals. The output 19 of the voltage threshold detector circuit 23 provides an alarm signal when the signal characteristic of a coincidence is absent on the output of the code recognition circuit 3.

Comme on le verra par la suite, cette absence provoque l'arrêt de la conduction de la bascule 20 et déclenche l'alarme 7 (figure 1). Le circuit d'alarme 5 comprend en outre une bascule monostable de maintien d'alarme minimum 24, connectée entre la sortie 21 de la bascule de déclenchement 20 et l'entrée 22 du circuit détecteur de seuil 23. Comme on le verra plus loin en détail, la durée de la période de conduction de cette bascule de maintien d'alarme, permet de fixer ia durée du signal d'alarme minimum appliqué au détecteur de seuil 23. Enfin, le circuit d'alarme 5 comprend en outre une porte logique 25 de type NON ET, à deux entrées 26, 27 qui sont reliées respectivement aux sorties de la bascule de déclenchement 20 et de la bascule de maintien minimum 24. La sortie de cette porte est reliée à l'entrée 22 du détecteur de seuil 23 ; l'association des bascules 20 et 24 de la porte logique 25, permet de fixer la durée de l'alarme lorsque l'intrusion est de courte durée, ou de maintenir cette alarme pendant toute la durée de l'intrusion, si celle-ci présente une durée supérieure à celle de la conduction de la bascule de maintien minimum 24.As will be seen later, this absence causes the conduction of the flip-flop 20 to stop and triggers the alarm 7 (FIG. 1). The alarm circuit 5 further comprises a monostable flip-flop for maintaining the minimum alarm 24, connected between the output 21 of the trigger flip-flop 20 and the input 22 of the threshold detector circuit 23. As will be seen below in detail, the duration of the conduction period of this alarm holding flip-flop makes it possible to set the duration of the minimum alarm signal applied to the threshold detector 23. Finally, the alarm circuit 5 also comprises a logic gate 25 of the NAND type, with two inputs 26, 27 which are respectively connected to the outputs of the trigger latch 20 and of the minimum holding latch 24. The output of this door is connected to the input 22 of the threshold detector 23 ; the combination of flip-flops 20 and 24 of logic gate 25 makes it possible to set the duration of the alarm when the intrusion is short-lived, or to maintain this alarm throughout the duration of the intrusion, if the latter has a duration greater than that of the conduction of the minimum holding lever 24.

Les moyens 15 qui permettent de retarder les impulsions, comprennent un compteur 28 dont l'entrée 14 reçoit les impulsions de chaque train et dont les sorties 29, 30, 31 sont respectivement reliées aux entrées de circuits 32 qui permettent de retarder respectivement les impulsions de chaque train, pour les amener en coïncidence avec la dernière impulsion du train. Le premier de ces circuits permet de retarder la deuxième impulsion de chaque train ; il est constitué par exemple par une première bascule monostable 33, apte à retarder la deuxième impulsion de manière à l'amener en coïncidence avec la dernière impulsion du train ; cette première bascule monostable est suivie d'une seconde bascule monostable 34 qui permet de mettre en forme cette impulsion retardée. Le deuxième de ces circuits qui comprend par exemple une porte ET 35 suivie d'une première bascule monostable 36, permet de décaler la troisième impulsion du train, de manière à l'amener en coïncidence avec la dernière impulsion de ce train. Ce retard est appliqué par une bascule monostable 36, dont la sortie est reliée à l'entrée d'une autre bascule monostable de mise en forme 37.The means 15 which make it possible to delay the pulses, comprise a counter 28 whose input 14 receives the pulses from each train and whose outputs 29, 30, 31 are respectively connected to the inputs of circuits 32 which make it possible respectively to delay the pulses of each train, to bring them into coincidence with the last pulse of the train. The first of these circuits makes it possible to delay the second pulse of each train; it is constituted for example by a first monostable rocker 33, capable of delaying the second pulse so as to bring it into coincidence with the last pulse of the train; this first monostable rocker is followed by a second monostable rocker 34 which makes it possible to shape this delayed pulse. The second of these circuits, which comprises for example an AND gate 35 followed by a first monostable rocker 36, makes it possible to offset the third pulse of the train, so as to bring it into coincidence with the last pulse of this train. This delay is applied by a monostable rocker 36, the output of which is connected to the input of another monostable shaping rocker 37.

Comme on le verra par la suite, on a supposé que les trains d'impulsions présentaient, respectivement quatre impulsions, mais ce nombre n'est pas limitatif. Les circuits de retard 32 comprennent un circuit dérivateur C, R, sur la quatrième impulsion, de façon à limiter sa durée d'efficacité à environ 200 µs, pour former ainsi le dernier signal de coïncidence. Cette quatrième impulsion n'a pas besoin d'être retardée.As will be seen later, it has been assumed that the pulse trains have four pulses, respectively, but this number is not limiting. The delay circuits 32 include a derivative circuit C, R, on the fourth pulse, so as to limit its duration of effectiveness to approximately 200 μs, to thus form the last coincidence signal. This fourth pulse does not need to be delayed.

Une autre entrée 38 du compteur 28 est reliée à un circuit logique de remise à zéro et de maintien de cette remise à zéro ; ce circuit est constitué par exemple, par la porte NON ET 39 et par des bascules monostables 40, 41.Another input 38 of the counter 28 is connected to a logic circuit for resetting and maintaining this reset; this circuit is constituted, for example, by the NAND gate 39 and by monostable flip-flops 40, 41.

Comme on le verra plus loin en détail, ce circuit logique permet de provoquer et de maintenir la remise à zéro du compteur 28 immédiatement après chaque détection de coïncidences. La durée du comptage est fixée par la durée de la période de conduction de la bascule monostable 41, tandis que la bascule 40 permet de maintenir la remise à zéro du compteur immédiatement après chaque détection de coïncidences, entre deux trains successifs d'impulsions.As will be seen below in detail, this logic circuit makes it possible to cause and maintain the resetting of counter 28 immediately after each detection of coincidences. The duration of the counting is fixed by the duration of the conduction period of the monostable flip-flop 41, while the flip-flop 40 makes it possible to maintain the reset of the counter immediately after each detection of coincidences, between two successive trains of pulses.

La figure 3 est un chronogramme des signaux présents en certains points caractéristiques de la barrière de l'invention. L'étude de ce chronogramme ya permettre de mieux comprendre le fonctionnement de cette barrière.FIG. 3 is a timing diagram of the signals present at certain characteristic points of the barrier of the invention. The study of this chronogram allows to better understand the functioning of this barrier.

Le diagramme a sur cette figure représente les trains d'impulsions successifs T, fournis par les moyens d'émission 1 de la figure 1.The diagram a in this figure represents the successive pulse trains T, supplied by the transmission means 1 of FIG. 1.

Dans le mode de réalisation décrit en exemple, il est supposé que l'émetteur fournit des trains successifs d'impulsions T, qui comportent respectivement quatre impulsions, chaque impulsion ayant une durée de 1 " et ces impulsions étant séparées par des intervalles de temps indiqués sur la figure. On suppose également que les trains d'impulsions se succèdent toutes les 18 ms et que le temps qui sépare la dernière impulsion d'un train de la première impulsion d'un train suivant est égal à 10,5 ms.In the embodiment described in example, it is assumed that the transmitter supplies successive trains of pulses T, which respectively comprise four pulses, each pulse having a duration of 1 "and these pulses being separated by indicated time intervals It is also assumed that the pulse trains follow each other every 18 ms and that the time between the last pulse of a train and the first pulse of a next train is equal to 10.5 ms.

Le diagramme b représenté les trains d'impulsions reçus par les moyens de réception 2. On suppose qu'aucune intrusion n'a eu lieu et qu'aucune impulsion parasite n'est venue perturber la barrière. Ce diagramme représente les impulsions à la sortie de la photodiode 10 ; elles ont par exemple une durée de 0,2 µs, qui passe à 0,6 " à la sortie de l'amplificateur et avant la mise en forme.Diagram b represents the pulse trains received by the reception means 2. It is assumed that no intrusion has taken place and that no parasitic pulse has disturbed the barrier. This diagram represents the pulses at the output of photodiode 10; for example, they have a duration of 0.2 µs, which changes to 0.6 "at the output of the amplifier and before shaping.

Le diagramme c représente les impulsions à la sortie des moyens d'amplification et de mise en forme 12. Chacune de ces impulsions a une durée de 50 pz par exemple.Diagram c represents the pulses at the output of the amplification and shaping means 12. Each of these pulses has a duration of 50 pz for example.

Le diagramme d représente le signal de sortie de la bascule monostable 41. Ce signal permet de fixer la durée du comptage des impulsions et permet également de déterminer, comme on le verra par la suite, les coïncidences. En l'absence de perturbations, ce signal a une durée de 7,7 ms par exemple ; il permet de déterminer les coïncidences dans un créneau de 200 µs, présentant un retard de 7,5 ms par rapport à la montée de la première impulsion du train.The diagram d represents the output signal of the monostable flip-flop 41. This signal makes it possible to fix the duration of the counting of the pulses and also makes it possible to determine, as will be seen hereinafter, the coincidences. In the absence of disturbances, this signal has a duration of 7.7 ms for example; it makes it possible to determine the coincidences in a 200 μs slot, having a delay of 7.5 ms with respect to the rise of the first pulse of the train.

Le diagramme e représente le signal de sortie de la bascule monostable 40. Ce signal qui est à un niveau haut en l'absence de perturbations présente une durée de 9,5 ms et permet de maintenir, pendant cette durée, la remise à zéro du compteur 28. La bascule monostable 40 est déclenchée par la combinaison du signal de sortie de la bascule 41 et du signal de sortie de la porte NON ET 39.The diagram e represents the output signal of the monostable flip-flop 40. This signal which is at a high level in the absence of disturbances has a duration of 9.5 ms and makes it possible to maintain, during this duration, the reset to zero of the counter 28. The monostable flip-flop 40 is triggered by the combination of the output signal of the flip-flop 41 and the output signal of the NAND gate 39.

Le diagramme f représente le signal de sortie de la bascule monostable 33. Dans l'exemple décrit, ce signal présente une durée de 5 ms correspondant au retard appliqué à la deuxième impulsion du train T.The diagram f represents the output signal of the monostable flip-flop 33. In the example described, this signal has a duration of 5 ms corresponding to the delay applied to the second pulse of the train T.

Le diagramme g représente la deuxième impulsion retardée, après sa mise en forme dans la bascule monostable 34, cette impulsion retardée présente une durée de 200 µs et elle est appliquée à l'une des entrées de la porte ET 16 du circuit logique de contrôle de coïncidences.Diagram g represents the second delayed pulse, after being shaped in the monostable flip-flop 34, this delayed pulse has a duration of 200 μs and it is applied to one of the inputs of AND gate 16 of the logic control circuit of coincidences.

Le diagramme h représente le signal de sortie de la bascule monostable 36 ; ce signal qui a durée de 3,5 ms, représente le retard appliqué à la troisième impulsion du train T.The diagram h represents the output signal of the monostable flip-flop 36; this signal, which has a duration of 3.5 ms, represents the delay applied to the third pulse of train T.

Le diagramme i représente la troisième impulsion du train T à la sortie de la bascule monostable 37, qui réalise une mise en forme de cette impulsion retardée par la bascule 36. Cette troisième impulsion mise en forme présente une durée de 200 ps ; elle est appliquée à l'autre entrée de la porte 16 du circuit de contrôle des coïncidences 16, 17, 18.Diagram i represents the third pulse of train T at the output of the monostable flip-flop 37, which realizes this pulse delayed by flip-flop 36. This third shaped pulse has a duration of 200 ps; it is applied to the other input of door 16 of the coincidence control circuit 16, 17, 18.

Le diagramme i représente le signal de sortie du circuit dérivateur R, C ; ce signal représente la dérivée par rapport au temps, de la quatrième et dernière impulsion du train ; cette impulsion n'est pas retardée mais simplement mise en forme, puisque les coïncidences sont déterminées à partir des fronts de montée de cette dernière impulsion.Diagram i represents the output signal of the branch circuit R, C; this signal represents the derivative with respect to time, of the fourth and last pulse of the train; this pulse is not delayed but simply shaped, since the coincidences are determined from the rising edges of this last pulse.

Dans l'invention, le traitement de cette dernière impulsion est effectué par un circuit dérivateur, de manière à ne pas introduire de retard parasite sur cette impulsion. Le signal de sortie de ce circuit dérivateur est appliqué à l'une des entrées de la porte ET 17 du circuit de contrôle des coïncidences ; l'autre entrée de cette porte ET reçoit le signal de sortie de la bascule monostable 41, c'est-à-dire le signal représenté sur le diagramme d. S'il y a coïncidence entre les différentes impulsions du train, retardées et traitées de la manière décrite, les signaux de sortie des portes ET 16 et 17 sont à un niveau haut ; ces signaux sont appliqués à la porte 18 du circuit de contrôle de coïncidences qui fournit, en cas de coïncidences, un signal caractéristique d'une durée de 200 (JLS. tel que représenté sur le diagramme k.In the invention, the processing of this last pulse is carried out by a differentiating circuit, so as not to introduce parasitic delay on this pulse. The output signal from this branch circuit is applied to one of the inputs of AND gate 17 of the coincidence control circuit; the other input of this AND gate receives the output signal from the monostable flip-flop 41, that is to say the signal shown in diagram d. If there is a coincidence between the different train pulses, delayed and processed in the manner described, the output signals from AND gates 16 and 17 are at a high level; these signals are applied to gate 18 of the coincidence control circuit which provides, in the event of coincidences, a characteristic signal with a duration of 200 (JLS. as shown in diagram k.

Lorsque toutes les coïncidences sont obtenues, un signal caractéristique, tel que celui qui est représenté sur le diagramme k est fourni par le circuit de contrôle de coïncidences à la bascule monostable 20 du circuit d'alarme 5 ; cette bascule, qui présente une période de conduction de 22 ms, supérieure à la durée de l'intervalle entre deux trains d'impulsions, mais inférieure à la somme des durées et de deux intervalles, soit 18 ms < 22 ms < 2 x 18 ms, présente alors une sortie dont le signal reste constamment à un niveau haut (niveau logique 1), tandis que la sortie de la bascule 24 de maintien d'alarme reste également à un niveau haut. Il en résulte qu'à la sortie de la porte NON ET 25, le signal logique est à un niveau bas (niveau 0). Ce signal de niveau bas est appliqué au relais 23 qui est maintenu collé. Si par contre, une intrusion de durée très faible, se produit entre les moyens d'émission et de réception, aucun signal de coïncidence n'est délivré à la sortie 4 du circuit logique de contrôle de coïncidences ; la sortie 21 de la bascule monostable de déclenchement 20 passe alors du niveau 1 au niveau 0 et il en résulte que le signal de sortie de la porte ET 25 passe au niveau 1, ce qui décolle le relais 23 et déclenche l'alarme 7. Pour toute perturbation de courte durée, le signal de sortie de la porte NON ET 25, est maintenu à un niveau haut pendant un temps qui est fixé par la durée de conduction de la bascule de maintien minimum 24 ; à titre d'exemple, ce temps est égal à 1 seconde et le signal de sortie de cette bascule, dans ce cas, est représenté sur le diagramme 1. On a supposé, en exemple dans ce cas, qu'il n'y a pas eu de coïncidences d'impulsions dans le train considéré et que le signal de sortie de la bascule de déclenchement d'alarme 20, au lieu de rester à un niveau haut, est retombé à un niveau bas, 22 ms après l'apparition de la première impulsion du train, tel que représenté sur le diagramme m.When all the coincidences are obtained, a characteristic signal, such as that which is represented on the diagram k is supplied by the coincidence control circuit to the monostable flip-flop 20 of the alarm circuit 5; this flip-flop, which has a conduction period of 22 ms, greater than the duration of the interval between two trains of pulses, but less than the sum of the durations and two intervals, ie 18 ms <22 ms <2 x 18 ms, then presents an output whose signal remains constantly at a high level (logic level 1), while the output of the flip-flop 24 for maintaining the alarm also remains at a high level. As a result, at the output of the NAND gate 25, the logic signal is at a low level (level 0). This low level signal is applied to relay 23 which is kept glued. If, on the other hand, an intrusion of very short duration occurs between the transmission and reception means, no coincidence signal is delivered to output 4 of the logic circuit for checking coincidences; the output 21 of the monostable trigger flip-flop 20 then goes from level 1 to level 0 and it follows that the output signal from the AND gate 25 goes to level 1, which takes off the relay 23 and triggers the alarm 7. For any short-term disturbance, the output signal from the NAND gate 25 is maintained at a high level for a time which is fixed by the conduction duration of the minimum holding flip-flop 24; by way of example, this time is equal to 1 second and the output signal of this flip-flop, in this case, is represented on diagram 1. It was supposed, in example in this case, that there is no coincidence of pulses in the train considered and that the output signal of the alarm trigger flip-flop 20, instead of remaining at a high level, fell to a low level, 22 ms after the appearance of the first pulse of the train, as shown in diagram m.

Lorsque la durée de la perturbation devient supérieure à une seconde, le signal de sortie de la bascule de déclenchement d'alarme 21, reste à un niveau 0 pendant toute la durée de cette perturbation ; il en résulte que le signal de sortie de la porte NON ET 25, reste à un niveau 1 pendant toute cette durée, bien que cette porte ait reçu sur son entrée 26 un signal de niveau 1 d'une durée de 1 seconde. Dans ce cas, le relais 23 reçoit pendant toute la durée de la perturbation, un signal de niveau 1 qui permet de déclencher l'alarme pendant toute cette durée.When the duration of the disturbance becomes greater than one second, the output signal of the alarm trigger flip-flop 21 remains at level 0 throughout the duration of this disturbance; it follows that the output signal from the NAND gate 25 remains at level 1 for the entire duration, although this gate has received at its input 26 a level 1 signal lasting 1 second. In this case, the relay 23 receives for the entire duration of the disturbance, a level 1 signal which makes it possible to trigger the alarm for this entire duration.

La barrière qui vient d'être décrite permet bien d'atteindre les buts mentionnés plus haut. En effet, toute impulsion parasite qui entre dans la séquence d'impulsions ou toute suppression d'impulsions du code produit un décalage dans le temps de comptage et perturbe les coïncidences, ce qui a pour effet de déclencher l'alarme. Les bascules monostables et les autres composants utilisés dans la barrière de l'invention ne sont pas décrits en détail. Les composants tels que bascules, diodes, photodiodes, ..., sont des dispositifs connus, disponibles dans le commerce.The barrier which has just been described makes it possible to achieve the goals mentioned above. Indeed, any parasitic pulse which enters the sequence of pulses or any suppression of pulses from the code produces a shift in the counting time and disturbs the coincidences, which has the effect of triggering the alarm. The monostable scales and the other components used in the barrier of the invention are not described in detail. Components such as flip-flops, diodes, photodiodes, etc., are known devices, available commercially.

La barrière de l'invention peut détecter des intrusions entre deux points voisins de 1 000 mètres.The barrier of the invention can detect intrusions between two points close to 1000 meters.

Il est également possible au lieu d'utiliser une diode laser à l'émission et un photodiode à la réception, d'utiliser un générateur d'impulsions électromagnétiques codées et un récepteur capable de détecter ces impulsions.It is also possible, instead of using a laser diode for transmission and a photodiode for reception, to use a generator of coded electromagnetic pulses and a receiver capable of detecting these pulses.

Claims (8)

1. Inviolable barrier for protection against intrusions, comprising means (1) for emitting pulsed signals modulated and encoded in a predetermined code, means (2) for receiving the emitted modulated and encoded signals, and means (3) for recognizing the predetermined code in the received signals, said recognition means (3) providing a characteristic signal at one output (4) each time the code is recognized, an alarm circuit (5) one input of which is connected to the output (4) of the code recognition means (3), said alarm circuit (5) providing an alarm signal in the absence of the characteristic signal, the code recognition means (3) comprising a system for detection of pulses by coincidence, and the modulated and encoded signals forming trains (T) of repetitive pulses, characterized in that the system (3) for detecting pulses by coincidence comprises means (32) for delaying, starting from the first pulse of each train, all pulses before the last pulse of the train, whereby to bring them into coincidence with the latter, and a circuit having logic gates (16, 17, 18) to control said coincidences, the circuit having logic gates providing said characteristic signal at an output (4) constituting the output of the detection system (3).
2. A barrier according to Claim 1, characterized in that the alarm circuit (5) comprises a monostable multivibrator (20) for tripping the alarm, one inlet (6) of which comprises the inlet of the alarm circuit (5), and one output (21) of which is connected to an input (22) of a detector circuit for a threshold potential (23), the duration of the conduction period of the alarm-tripping monostable multivibrator (20) being greater than the duration of the interval separating two pulse trains (T) while being less than the sum of the duration of two intervals, the output (19) of the detector circuit (23) providing an alarm signal when the characteristic signal is absent, said absence producing cessation of conduction of the alarm-tripping monostable multivibrator (20).
3. Barrier according to Claim 2, characterized in that the alarm circuit (5) additionally comprises a monostable multivibrator (24) for maintaining a minimum alarm, connected between the output (21) of the alarm-tripping multivibrator (20) and the input (22) of the threshold detector circuit (23), the duration of the conduction period of said alarm maintenance multivibrator (24) enabling a minimum duration to be fixed for the alarm circuit.
4. Barrier according to Claim 3, characterized in that the alarm circuit (5) additionally comprises a logic gate (25) having two inputs, said inputs being respectively connected to the outputs of the alarm-tripping multivibrator (20) and the minimum maintenance multivibrator (24), the output of said gate (25) being connected to the input (22) of the threshold detector (23), such that the duration of the alarm signal is equal to the duration of an intrusion, when said intrusion has a duration greater than that of conduction of the minimum alarm maintenance multivibrator (24).
5. Barrier according to Claim 1, characterized in that the pulse delay means comprise a counter (28) of which one input (14) receives the pulses of each train (T) and whose outputs (29, 30, 31) are respectively connected to the inputs of circuits (32) permitting respective retardation of the pulses of each train, to bring them into coincidence with the last impulse of the train, another input (38) of said counter (28) being connected to a logic circuit (39, 40, 41) for resetting to zero and maintaining setting at zero, said logic circuit being adapted to produce and maintain the resetting to zero of the counter, immediately after each detection of coincidence between two successive pulse trains.
6. A barrier according to any one of Claims 1 to 5 characterized in that the emission means (1) comprise a laser diode (8) commanded by a modulator (9) of encoded pulses, and in that the receiving means (2) comprise a photodiode (10) one output of which is connected to an amplification and shaping circuit (12), the output of this circuit constituting the output of the receiving means (2).
7. A barrier according to Claim 6, characterized in that the amplification and shaping circuit (12) comprises a non-linear «all or nothing amplifier, from a threshold level above the peak level of total noise of the receiver and amplifier, said threshold being fixed by a comparator and adjustable as a function of the maximum tolerable temperature of operation of the barrier.
8. A barrier according to any one of Claims 1 to 6 characterized in that the emission means (1) comprises a generator of coded electromagnetic pulses.
EP81401559A 1980-10-13 1981-10-08 Inviolable barrier for the protection against intrusions Expired EP0050549B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8021825 1980-10-13
FR8021825A FR2492136A1 (en) 1980-10-13 1980-10-13 INVIOLABLE BARRIER FOR PROTECTION AGAINST INTRUSIONS

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EP0050549A1 EP0050549A1 (en) 1982-04-28
EP0050549B1 true EP0050549B1 (en) 1985-07-17

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US (1) US4465998A (en)
EP (1) EP0050549B1 (en)
JP (1) JPS5797196A (en)
CA (1) CA1191227A (en)
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FR (1) FR2492136A1 (en)

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GB2137388A (en) * 1983-03-30 1984-10-03 Bruce Stanley Gunton Improvements relating to a security system
US4583082A (en) * 1983-06-09 1986-04-15 Igt Optical door interlock
US4692752A (en) * 1984-08-27 1987-09-08 Sentrol, Inc. Moisture detector
US4633235A (en) * 1984-12-20 1986-12-30 Degennaro Charles S Optical cable security system with standby and automatic re-arming features
GR861382B (en) * 1985-11-13 1987-02-06 Pelta Elettronica S P A System for remote control of the antitheft protection devices of a property
US4829174A (en) * 1986-09-29 1989-05-09 General Motors Corporation Flexible tube optical intrusion detector
GB8829892D0 (en) * 1988-12-22 1989-09-13 Racal Guardall Scotland Radiation detection arrangements and methods
JPH032325U (en) * 1989-05-29 1991-01-10
US5144286A (en) * 1990-08-06 1992-09-01 Allen-Bradley Company, Inc. Photosensitive switch with circuit for indicating malfunction
JPH0561794U (en) * 1992-01-27 1993-08-13 横河電機株式会社 Liquid crystal display
GB2361308B (en) * 1999-03-17 2002-04-10 British Telecomm Detection system

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US2984789A (en) * 1958-08-13 1961-05-16 Bell Telephone Labor Inc Pulse monitoring circuit
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US4465998A (en) 1984-08-14
JPS5797196A (en) 1982-06-16
DE3171411D1 (en) 1985-08-22
CA1191227A (en) 1985-07-30
EP0050549A1 (en) 1982-04-28
FR2492136A1 (en) 1982-04-16
JPS6351317B2 (en) 1988-10-13
FR2492136B1 (en) 1983-12-09

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