EP0036620B1 - Halbleiterbauelement und Verfahren zu seiner Herstellung - Google Patents

Halbleiterbauelement und Verfahren zu seiner Herstellung Download PDF

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Publication number
EP0036620B1
EP0036620B1 EP19810101993 EP81101993A EP0036620B1 EP 0036620 B1 EP0036620 B1 EP 0036620B1 EP 19810101993 EP19810101993 EP 19810101993 EP 81101993 A EP81101993 A EP 81101993A EP 0036620 B1 EP0036620 B1 EP 0036620B1
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Prior art keywords
layer
region
polycrystalline silicon
type
semiconductor region
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French (fr)
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EP0036620A3 (en
EP0036620A2 (de
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Yoshitaka Sasaki
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Toshiba Corp
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Toshiba Corp
Tokyo Shibaura Electric Co Ltd
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Priority claimed from JP3577580A external-priority patent/JPS56133864A/ja
Priority claimed from JP55182336A external-priority patent/JPS57106067A/ja
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Publication of EP0036620A2 publication Critical patent/EP0036620A2/de
Publication of EP0036620A3 publication Critical patent/EP0036620A3/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor

Definitions

  • the present invention relates to a semiconductor device and a method for fabricating the same.
  • a bipolar transistor suitable for use within the high frequency range or suitable as a high speed switching element is required to have a great gain band product.
  • Most of the silicon transistors which are currently used are of the planar type, and their emitters and bases are formed by impurity diffusion. In such a case, when the dimension of the emitter is small, the junction plane of the emitter and the base becomes curved, and the effective base transit time depends not only on the base width but also on the collector-base junction depth. Accordingly, for improving the gain band product of the bipolar transistor, it is necessary to reduce the base width as well as the collector-base junction depth. Thus, the problem is to how to realize a shallow diffusion junction.
  • a conventional bipolar npn transistor is of the structure shown in Fig. 1.
  • On a p--type silicon substrate 1 are formed an n +- type buried layer 2 and an n-type epitaxial layer 3.
  • a p +- type isolation region 4 for element isolation is formed in the epitaxial layer 3.
  • a p-type base region 5 is formed at the part of the island epitaxial layer 3 isolated by the isolation region 4, and an n +- type emitter region 6 is formed in the base region 5.
  • a diffusion layer 7 reaching to the n +- type buried layer 2 for connection with the collector is formed in another part of the epitaxial layer 3.
  • An oxide film 8 is formed on the n-type epitaxial layer 3 by thermal oxidation.
  • Aluminum electrodes 10, 11 and 12 for connection with the emitter region 6, the base region 5, and the diffusion layer 7 for connection with the collector are formed thereover through contact holes 9a, 9b and 9c, respectively.
  • the base resistance increases accordingly.
  • the base resistance depends on the distance I between the emitter side end of the base contact hole 9b and the emitter region 6. This distance I is determined by the relative positions of the diffusion windows for the emitter region 6 and the base contact holes. This relation is in turn determined by the photoetching technique. With the current photoetching technique, it is difficult to make the distance I less than 2 ⁇ m. This places a limit on the reduction of the base resistance.
  • I 2 L Integrated Injection Logic
  • the epitaxial layer 3 is isolated by the p +- type isolation region 4.
  • a p-type injector 13 and a p-type base region 14 are formed in the epitaxial layer 3.
  • a plurality of n +- type collector regions 15a, 15b are formed in the base region 14.
  • the oxide film 8 is formed on the epitaxial layer 3 by thermal oxidation.
  • An 1 2 L of such a structure is a bipolar logic element of a composite structure incorporating a vertical npn transistor of the reverse operation type wherein the emitter and the collector of a normal transistor are reversed, and a lateral pnp transistor using the base of the vertical npn transistor as the collector.
  • the vertical npn transistor as the inverter is inverted, the emitter-base junction area is vastly greater than the collector-base junction area so that a sufficiently high speed operation of the bipolar element may not be attained.
  • I 2 L which is free of such defects is described in IEDM Technical Digest (1979), pp. 201 to 204, "Sub-Nanosecond Self-Aligned I 2 L/MTL Circuits".
  • a polycrystalline silicon layer in which is doped an n +- type impurity to a high concentration is used as the collector region in this I 2 L.
  • the base contact holes and the collector region are formed by the self-aligning technique utilizing the thickness difference with the silicon oxide film.
  • the base region exposed at the surface of the substrate is covered with a metal to decrease the base resistance, allowing a structure such that the ratio of the emitter-base junction area to the collector-base junction area may approach 1.
  • This I 2 L shows the best performance of 0.8 nsec in minimum propagation delay time among the conventional I 2 Ls. However, this I 2 L also has many problems. The method for fabricating this element will be described in detail with reference to the attached drawings.
  • an n-type epitaxial layer 23 is formed in an n + -type semiconductor substrate 22a.
  • a high-concentration n +- type semiconductor film 22b is formed at the surface of the substrate 22a to provide the emitter region (Fig. 3A).
  • a silicon nitride layer 24 is deposited to a thickness of 100 nm, as shown in Fig. 3B.
  • the n-type epitaxial layer 23 thereunder is selectively etched.
  • a heat treatment is performed to form a silicon oxide layer 25 of about 1.0 to 1.5 ⁇ m thickness on the etched part. Since this silicon oxide layer 25 is formed to surround the periphery of the 1 2 L gate, it is also called the oxide film collar or the oxide isolation layer.
  • This silicon oxide layer functions to isolate between the gates of the 1 2 L and to improve the injection efficiency of the minority carriers injected from the emitter to the base.
  • a silicon oxide layer is again formed to a thickness of 500 nm.
  • a silicon oxide layer 26 is formed (Fig. 3C).
  • an arsenic-doped polycrystalline silicon film 29 is deposited to a thickness of 300 nm, and a CVD silicon oxide layer (CVD-Si0 2 ) 30 is deposited thereover to a thickness of 300 nm.
  • the CVD-Si0 2 is patterned by the photoetching technique.
  • the selectively left portion of the arsenic-doped polycrystalline silicon film 29 exists on the base region 27 for forming the collector region of the 1 2 L, and is used for connection with the collector electrode.
  • the structure is thermally oxidized at a low temperature (700 to 900°C).
  • a silicon oxide film 32b of about several ten nm thickness is formed on the base region 27 and the injector region 28, and a silicon oxide film 32a of about 100 to 200 nm thickness is formed on the side surface of the arsenic-doped polycrystalline silicon film 29.
  • the growing speed of the high-concentration n +- type semiconductor layer is greater by a factor of several to several tens than that of the low-concentration n +- type semiconductor layer when oxidized at a low temperature (700 to 900°C).
  • ion implantation of high-concentration p +- type ions is performed to form the injector region 28 and an outer base region 27' by diffusion (Fig. 3E).
  • Fig. 3F shows a plan view of Fig. 3F
  • Fig. 5 shows a sectional view along the line V-V of Fig. 4.
  • the electrodes of the base, the injector, and the emitter may be formed from the metal electrode layer, and the collector electrode may be formed from the arsenic-doped polycrystalline silicon layer, providing the various advantages described above.
  • this method of fabricating an 1 2 L has various problems to be described below.
  • the arsenic-doped polycrystalline silicon film 29 is thermally oxidized at a low temperature (700 to 900°C) in the process shown in Fig. 3E, the wiring width becomes smaller and the wiring resistance becomes greater accordingly.
  • the silicon oxide film 32a obtained by low-temperature oxidation of the n +- type semi- conductor layer of high concentration is formed to be several times thicker than the silicon oxide film 32b formed on the p--type semiconductor layer of low impurity concentration as the temperature for oxidation becomes lower.
  • a thick silicon oxide film is inferior in denseness, resulting in inferior insulating characteristics.
  • the silicon oxide film obtained by oxidizing at 800°C the n +- type polycrystalline silicon layer of high impurity concentration is etched in an HF-type solution, the insulating characteristics are very inferior.
  • a silicon oxide film of 100 nm thickness formed by oxidation of a single-crystalline silicon layer at a high temperature (above 1,000°C) has a breakdown voltage of 80 to 90 V
  • the silicon oxide film of 200 nm thickness described above has a breakdown voltage of 10 to 20 V or less, occasionally becoming zero.
  • the silicon oxide film 32a grown on both sides of the arsenic-doped polycrystalline silicon film 29 over the base region 27 formed in the single crystalline silicon layer, grows less at the contact part with the single crystalline silicon layer (base region 27) and is recessed. Due to this, when the silicon oxide film 32b at both sides of the arsenic-doped polycrystalline silicon film is etched by an HF type etchant, the silicon oxide film 32a of the arsenic-doped polycrystalline silicon film 29 is inferior in denseness and weakly resistant to the etchant.
  • the contact part with the base region 27 is thinner as compared with other parts, the lower side surface of the arsenic-doped polycrystalline silicon film 29 of the collector region 31 is etched as shown in FIg. 6B, exposing the n +- type collector region 31 formed by using the polycrystalline silicon film 29 as a diffusion source from the side surface of the polycrystalline silicon film 29.
  • the electrode 33 contacts the exposed part of the collector region 31, thereby short-circuiting of the base and the collector.
  • a method for fabricating a semiconductor device comprising the steps of:
  • a method for fabricating a semi- conductor device comprising the steps of:
  • a semiconductor device comprising:
  • the present invention has been made based on the finding that, when silicon is epitaxially grown on an insulating film, such as a silicon nitride layer or an alumina layer, formed on a semiconductor substrate and having a predetermined pattern and oxidation resistance characteristics, a polycrystalline silicon layer is formed on the insulating film and a single-crystalline silicon layer is formed on the semiconductor layer; the polycrystalline silicon layer alone is removed and a projection consisting of the single-crystalline silicon layer is formed when the epitaxial layer thus obtained is etched; and an ooening is formed in the region of the semi- conductor substrate in alignment with the oxide film on the surface of the projection, when an oxide film is formed on the surface of this projection and the insulating film is removed.
  • an insulating film such as a silicon nitride layer or an alumina layer
  • This example is an application of the method of the present invention to a method for fabricating a bipolar npn transistor.
  • an n +- type buried layer 42a is formed in a p--type semiconductor substrate 41, and an n-type epitaxial growth layer 43 is formed thereover.
  • a p l- type isolation layer 44 for isolating this n-type layer 43 is formed by diffusion.
  • an n +- type diffusion layer 42b reaching to the n +- type buried layer 42a for connection with the collector is formed by introducing an n-type impurity from a predetermined region of the surface of the n-type epitaxial layer 43.
  • a silicon oxide film 45 is formed to a thickness of 500 nm. The silicon oxide film 45 is partially removed by photoetching.
  • a p-type region 46 is formed as a base region by introducing a p-type impurity from this opening.
  • An oxidation-resistive mask, e.g. silicon nitride film 47 of 100 nm thickness is deposited on the silicon oxide film 45 and the p-type region 46 to remove the desired part.
  • Vapor epitaxial growing of undoped silicon is performed thereover.
  • an undoped single-crystalline silicon layer 48 of 500 nm thickness is formed on the exposed part of the p-type region 46 through the opening of the silicon nitride film 47, and an undoped polycrystalline silicon layer 49a of 500 nm thickness is formed on the silicon nitride film 47.
  • a doped silicon layer may alternatively be formed in place of the undoped silicon layer during vapor growth.
  • part of the polycrystalline silicon layer 49a that is, the part for forming the connecting wiring for the emitter electrode, is covered with an etching-resistive mask, e.g. a photoresist film 50 as shown by the plan view of Fig. 8A.
  • an etchant with a great difference in its etching rates for polycrystalline silicon and slngle-crystalline silicon, the polycrystalline silicon layer 49a is removed by etching to leave the single-silicon layer 58 projecting from the surface.
  • part 49b of the polycrystalline silicon layer 49a covered with the photoresist film is also left so that the single crystalline silicon layer 48 and the remaining polycrystalline silicon layer 49b are connected in a manner as shown in Fig. 8B.
  • the remaining polycrystalline silicon layer 49b is used as the connection wiring for the emitter electrode.
  • a very high precision is not required in the alignment for the formation of the connection wiring of the emitter electrode described above. Thus, a small error does not pose any problem to the fabrication of elements of finer structure.
  • the photoresist may be shifted to the part 48 as the base region.
  • An etchant having a great difference between its etching rates for polycrystalline silicon and single-crystalline silicon may include a liquid mixture of HF, HN0 3 , and CH 3 COOH; and a mixture of HF, HN0 3 , CH 3 COOH and H 2 0.
  • the etching rate for polycrystalline silicon with such an etchant is several ten times that for the single-crystalline silicon.
  • the etching rate also varies depending upon the kind and concentration of the impurity in the polycrystalline silicon or single-crystalline silicon.
  • the selective etching described above may also be performed by the dry etching method using a gas etchant containing fluorocarbon such as Freon (RTM).
  • an n +- type impurity of high concentration is introduced into the single-crystalline silicon layer 48 by thermal diffusion or ion implantation to form an n +- type semiconductor layer 51.
  • the high-concentration n +- type impurity is also introduced in the connecting wiring for the emitter electrode. It is also possible to perform this doping step of the n +- type impurity before etching.
  • the surface thereof is oxidized. Since the silicon nitride film 48 is not oxidized, the projecting n l- type single-crystalline silicon layer 51 and the n +- type polycrystalline silicon layer 49b are oxidized to provide silicon oxide films 52 and 53 of 300 nm thickness as shown in Figs. 7E and 9B.
  • the growing temperature of the silicon oxide film may be within the range of 950 to 1,000°C or more. By oxidation at such a high temperature, the silicon oxide films 52 and 53 of improved denseness and insulating characteristics are formed on the surfaces of the n +- type polycrystalline silicon layer 49b and the n +- type single-crystalline silicon layer 51. It is possible to control the thickness of the silicon oxide films to a desired value by using arsenic or antimony as the n +- type impurity so that the control of the current-amplification factor becomes extremely easy.
  • the base contact holes and the emitter region are formed by self-alignment by removing the silicon nitride film 47 by wet etching using a hot phosphoric acid, or by dry etching using a Freon-type etchant.
  • a metal layer is coated to a thickness of about 1.0 ,um and is patterned to form a base electrode 54, a collector electrode 55, and an emitter electrode 56 to complete a bipolar npn transistor as shown in Fig. 7F.
  • Fig. 9A is a top view of this transistor.
  • Fig. 7F is a sectional view along the line A-A of Fig. 9A
  • Fig. 9B is a sectional view along the line B-B of Fig.
  • the relation of the emitter side end of the base contact hole and the emitter region is determined by the thickness of the silicon oxide film 52 formed on the surface of the projecting emitter region.
  • the distance between the emitter end of the base contact hole and the emitter region was required to be at least 3 ⁇ m, which is the sum of 2 ⁇ m required for error in alignment and 1 ⁇ m required for the side etching of the silicon oxide film in the contact hole.
  • the method of the present invention no limits are imposed on the finer structure of the element by the alignment error by the photoetching, and it is possible to form the base contact hole and the emitter region with the shortest distance therebetween correctly at a high yield. Accordingly, the base resistance may be minimized even in the case of an element having a shallow base region for high-speed operation. Furthermore, most of the surface of the base region 46 is covered by the metal layer 54. Thus, the base resistance becomes still smaller, resulting in an element of higher gain band product.
  • the element of the present invention When compared with the 1 2 L element described in "Sub-Nanosecond Self-Aligned I 2 L/MTL Circuits" hereinabove, the element of the present invention exhibits excellent reliability and performance. Further, since the edge of the projection does not overhang when forming this projection but may be formed smooth, disconnection of the base electrode layer or disconnection of the other interconnection layer crossing thereover is effectively prevented. Since the surface of the projection is oxidized at a high temperature for a long period of time, a silicon oxide film with improved denseness and insulating characteristics is formed between the emitter region and the base electrode. Short-circuiting between the base and the emitter (between the base and the collector in the case of an 1 2 L) seldom occurs.
  • the base contact hole may further be easily formed by wet etching the silicon nitride film with a hot phosphoric acid or by dry etching it with Freon or the like. It is possible to control the thickness of the single-crystalline silicon layer and the polycrystalline silicon layer with a high precision, i.e., to make the single-crystalline silicon layer thicker and the polycrystalline silicon layer thinner or vice versa, by varying the conditions of the vapor growth. For this reason, it is possible to reduce the emitter dynamic resistance and the resistance of the emitter electrode.
  • emitter dip which is one of the factors which obstruct the high-speed operation of the device and which is a common defect of conventional transistors, is avoided according to the method of the present invention.
  • a conventional semiconductor device of the type described hereinabove so-called “emitter dip” is caused according to which the base region immediately below the emitter region is recessed because the emitter diffusion is performed in the diffusion region after the base diffusion.
  • the emitter dip greatly adversely affects the performance of the high-speed switching element. Since the projection for forming the emitter region is formed by the epitaxial growth technique in the method of the present invention, the emitter impurity need not be diffused deeply in the base region; thus, the emitter dip is avoided.
  • a bipolar npn transistor obtained by this example is shown in Fig. 10.
  • the base region is of double-base structure consisting of a p--type semiconductor layer (inner base) 46a and a p +- type semiconductor layer (outer base) 46b, and the emitter region 51 is formed adjacent to the p'-type semiconductor layer 46a, providing a bipolar npn transistor with reduced base- emitter junction capacity. Since the impurity concentration of the inner base 46a is low, a great current-amplification factor may be obtained.
  • the method of this example is substantially the same as that of Example 1 except for the double base structure. The method for fabricating the double-base structure will be described with reference to the method for fabricating an 1 2 L in Example 3.
  • This example illustrates a case wherein the method of the present invention is applied to the method for fabricating an 1 2 L.
  • the base employs the double-base structure as in the case of Example 2.
  • an n-type epitaxial layer 63 of 0.5 Q-cm resistivity and 2 ⁇ m thickness is formed on an n +- type semiconductor substrate 62a. Thereafter, a silicon oxide film (not shown) of 500 nm thickness is formed over the entire surface. After removing the part corresponding to the emitter region, an n-type impurity is introduced through this opening to form an n +- type semiconductor layer 62b as the emitter (GND) region, and the silicon oxide film is removed.
  • a silicon nitride film 65 is deposited to a thickness of 100 nm as shown in Fig. 11B.
  • the part of the n-type epitaxial layer 63 to become the isolation region is etched using the silicon nitride film 65 as a mask.
  • a silicon oxide film 64 of about 1.0 to 1.5 ⁇ m thickness is formed on the etched part of the epitaxial layer 63. This silicon oxide film 64 is called an oxide film collar, and surrounds the 1 2 L.
  • silicon oxide film 65 After removing the silicon nitride film 65, another silicon oxide film of 500 nm thickness is formed and is then patterned by photoetching to provide a silicon oxide film 66.
  • an undoped epitaxial layer of 500 nm thickness is formed.
  • a single-crystalline silicon layer 68 is formed on the exposed n-type epitaxial layer 63, and a polycrystalline silicon layer 69 is formed on the silicon nitride film 67.
  • part of the polycrystalline silicon layer 69 is covered with a etching-resistive mask, e.g. a photoresist film.
  • a etching-resistive mask e.g. a photoresist film.
  • the polycrystalline silicon layer 69 is removed to leave the single-crystalline silicon layer 68 projecting from the surface.
  • the part of the polycrystalline silicon layer 69 covered by the photoresist film also remains unetched.
  • the remaining parts of the single-crystalline silicon layer 68 and of the polycrystalline silicon layer 69 are connected as shown in Fig. 8B.
  • a p--type impurity into the single-crystalline silicon layer 68 is performed to provide an inner base 70a of the J 2 L. Since the thickness of the projecting single-crystalline silicon layer is about 0.5 ,um and the inner base diffusion layer is formed to a depth of about 0.2 ⁇ m in the n-type epitaxial layer 63, the total thickness of this diffusion layer is about 0.7 lu m. Then, an n +- type semiconductor layer 71 used as the collector is formed on the surface of the diffusion layer 70a by diffusing an n +- type impurity such as arsenic. This condition is shown in Fig. 11 E. The polycrystalline silicon layer for connection with the collector electrode comprises the n l- type region throughout the entire thickness. This is because the diffusion rate for the polycrystalline silicon layer is greater than that for the single-crystalline silicon layer.
  • the surface of the projection is oxidized. Since this oxidation is performed at a high temperature of 1,000°C, the film thickness and quality do not depend much on the kind and concentration of the impurity in the substance to be oxidized and whether or not the substance to be oxidized is poly- or single-crystalline silicon.
  • an oxide film 72 of about 300 nm thickness is formed on the n +- type single-crystalline silicon, and the oxide film 72 of about 320 to 330 nm thickness is formed on the n +- type polycrystalline silicon. Both of these oxide films are dense and have superior insulating characteristics.
  • the silicon nitride film 67 is removed.
  • a p-type impurity is introduced in the n-type epitaxial layer 63 by ion implantation or diffusion to form an injector region 73 and an outer base region 70b as shown in Fig. 11 G. All the contact holes are opened and metal electrode layers 74a, 74b and 74c of about 1.0 ⁇ m thickness are formed to complete the 1 2 L.
  • the 1 2 L fabricated in the manner described above has, in addition to the advantages of the devices in Examples 1 and 2, an additional advantage according to which the ratio of the emitter-base junction area to the collector-base junction area may be made near 1. Furthermore, since there is no alignment error due to photoetching in the formation of the injector, the base, and the collector which otherwise obstructs the fine structure of the element in this Example, 1 2 Ls of high denseness and high performance may be fabricated at a high yield. Multi-interconnection may also be realized by using polycrystalline silicon for the interconnection layer, facilitating fabrication of LSls of high integration.
  • Example 2 Since the semiconductor device of Example 2 is fabricated in a manner similar to that of Example 3, an LSI of high integration incorporating both a high-speed 1 2 L and a high-speed ECL (Emitter Coupled Logic), for example, may be easily fabricated by forming the 1 2 L and the linear circuit on a single chip. An example of the semiconductor device thus obtained is shown in Fig. 12.
  • ECL Electrode Coupled Logic
  • VCEO high-voltage resistance
  • This example illustrates a case wherein an 1 2 L is fabricated by forming the projection utilizing not only the difference in the etching rates depending on whether single-crystalline silicon or polycrystalline silicon is involved, but also the difference in the etching rates depending on the kind and concentration of the impurity, and the jumper interconnection layer is formed simultaneously with the formation of the projection.
  • n-type silicon epitaxial layer 102 is formed on the n +- type silicon layer 101 and an n +- type diffusion layer 103 is formed on the epitaxial layer 102, they are subjected to selective oxidation to form a silicon oxide film 105 as an oxide film collar or an oxide insulating layer.
  • a silicon nitride film 109 of 100 nm thickness as an oxidation-resistive insulating film, and an AsSG film 110 of 150 nm thickness containing an impurity, are formed in the order named on the entire surface of the structure (Fig. 14A).
  • parts of the AsSG film 110 to become the collector connecting electrode and the jumper wiring are selectively etched away to form an AsSG film pattern 111.
  • the parts of the silicon nitride film 109 covered with the AsSG pattern 111 are selectively etched to form an opening. Boron is thermally diffused into the n-type silicon epitaxial layer 102 through the opening to form a p-type inner base region 107 (Fig. 14B).
  • Silicon is then epitaxially grown on the entire surface in a boron atmosphere.
  • a p-type single-crystalline silicon layer 124 of 400 nm thickness and of low concentration is formed on the part which is directly in contact with the p-type inner base region 107 consisting of the silicon epitaxial layer
  • a low-concentration boron-doped polycrystalline silicon layer 113a of the same thickness is formed on the silicon nitride film 109
  • a high-concentration arsenic-doped polycrystalline silicon film 113b in which is diffused arsenic at high concentration from the pattern 111 is epitaxially formed on the AsSG film pattern 111 as shown in Fig. 14C.
  • the type etchant having an etching selection ratio between a low-concentration boron-doped polycrystalline silicon.
  • the etching rate of the high concentration arsenic-doped polycrystalline silicon film 113b is as fast as several ten times that of the low-concentration boron-doped polycrystalline silicon 113a, and is still faster than that of the single-crystalline silicon film 124.
  • the high concentration arsenic-doped polycrystalline silicon film 113b is selectively etched to form a projecting p-type single crystalline silicon film 124 formed integral with the p-type inner base region 107, a p-type polycrystalline silicon film pattern (not shown) formed integral therewith, and a p-type polycrystalline silicon pattern 114. Thereafter, the AsSG film 111 is removed.
  • n +- type collector region 116 is formed on the projecting p-type single-crystalline silicon film 124 formed by diffusing arsenic, while converting the p-type polycrystalline silicon pattern (not shown) formed integral with the single- crystal silicon film 124 into an n +- type pattern (114a in Fig. 15), and converting the p-type polycrystalline silicon pattern 114 into an n +- type polycrystalline silicon pattern 114b.
  • the structure is then subjected to thermal oxidation at 950°C. Then, a single-crystalline silicon as shown in Fig.
  • an n +- type polycrystalline silicon pattern (not shown) formed integral therewith, and oxide films 115a and 115b which are dense and superior in insulating characteristics and surrounding the pattern 114b are formed.
  • Introduction of the oxidant into the silicon epitaxial film 102 in which is formed the silicon nitride film 109 is prevented.
  • the n +- type polycrystalline silicon pattern (not shown) formed integral therewith and located on the silicon oxide film 105 functions as a collector-connecting electrode
  • the n +- type polycrystalline silicon pattern 114b which is on the silicon nitride film 109 and the silicon oxide film 105, functions as a jumper wire.
  • Etching is then performed, with a wet etchant such as hot phosphoric acid which is used as an etchant of silicon nitrides, or with a Freon-type dry etchant, to selectively remove the silicon nitride film 109, and to form a single-crystalline silicon projection, an n +- type polycrystalline silicon pattern (not shown) formed integral therewith, oxide films 115a and 115b surrounding an n +- type polycrystalline silicon pattern 114b as a jumper wire, and window openings 117a to 117d self-aligned with respect to the thermally oxidized film 106.
  • a wet etchant such as hot phosphoric acid which is used as an etchant of silicon nitrides, or with a Freon-type dry etchant
  • Boron of high concentration is ion-implanted using the window openings 117a to 117d described above as ion implantation windows to form a p +- type injection region 108 in the silicon epitaxial layer 102 exposed through the window opening 117a, and to form a p +- type outer base region 118 in the silicon epitaxial layer 102 exposed through the window openings 117b to 117d (Fig. 14F).
  • the 1 2 L is completed by forming a base-connecting AI electrode 119, an injector-connecting AI electrode 120 and an emitter-connecting AI electrode 122 (Figs. 14G, 15 and 16).
  • Fig. 15 is a plan view of Fig. 14G
  • Fig. 16 is a sectional view along the line X-X of Fig. 15.
  • a projection or a single-crystalline silicon layer is formed by epitaxial growth of silicon.
  • the method of providing the single-crystalline silicon layer is not limited to this.
  • An energy beam such as a laser beam may be applied onto a polycrystalline silicon layer or amorphous silicon layer deposited by CVD or PVD, thereby changing that portion of the polycrystalline silicon layer or amorphous silicon layer which contacts the semiconductor substrate to a single crystalline silicon layer.
  • bipolar transistors are fabricated in the above examples, the present invention is not necessarily limited to this application but may be applied to MOS transistors, field-effect transistors, and so on.

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Claims (13)

1. Verfahren zur Herstellung einer Halbleitervorrichtung, dadurch gekennzeichnet, daß man auf einer Halbleiterschicht mit einem ersten Halbleiterbereich eines ersten Leitfähigkeitstyps eine erste isolierende Schicht oder Lage (45) mit einer oder mehreren Öffnung(en) ausbildet, zur Bildung eines zweiten Halbleiterbereichs (46) in der Halbleiterschicht über die Öffnung(en) der ersten isolierenden Schicht (45) ein Fremdatom eines zweiten Leitfähigkeitstyps einführt, eine oxidationsbeständige und die erste isolierende Schicht (45) und einen Teil des zweiten Halbleiterbereichs (46) bedeckende zweite isolierende Schicht (47) erzeugt, auf der zweiten isolierenden Schicht (47) eine polykristalline Siliziumschicht (49a) und auf dem freiliegenden zweiten Halbleiterbereich (46) eine Siliziumeinkristall-Schicht (48) ausbildet, die (durch epitaxiales Aufwachsen) gebildete Schicht mit einem das polykristalline Silizium rascher als den Siliziumeinkristall (weg)ätzenden Ätzmittel ätzt, um einen aus dem Siliziumeinkristall (48) und dem angrenzenden Teil (49b) des polykristallinen Siliziums (49a) bestehenden Vorsprung zu bilden, zur Ausbildung eines dritten Halbleiterbereiches (51) in dem Vorsprung aus dem Siliziumeinkristall in diesen ein Fremdatom des ersten Leitfähigkeitstyps einführt, auf der Oberfläche des Vorsprungs eine dritte isolierende Schicht (52) ausbildet, zur Bildung einer Elektrodenanschlußöffnung des zweiten Halbleiterbereichs (45) die zweite isolierende Schicht (47) (weg)ätzt und eine Verbindungselektrodenschicht (54), die mit dem zweiten Halbleiterbereich (46) über die Elektrodenanschluß- öffnung in Verbindung steht und gegen den dritten Halbleiterbereich (51) mittels der dritten isolierenden Schicht (52) isoliert ist, erzeugt.
2. Verfahren zur Herstellung einer Halbleitervorrichtung, dadurch gekennzeichnet, daß man auf einer Halbleiterschicht (63) mit einem ersten Halbleiterbereich eines ersten Leitfähigkeitstyps eine erste isolierende Schicht oder Lage (66) mit einer oder mehreren Öffnung(en) ausbildet, eine oxidationsbeständige und die erste isolierende Schicht (66) und einen Teil der Halbleiterschicht bedeckende Isolierschicht (67) erzeugt, auf der zweiten isolierenden Schicht (67) eine polykristalline Siliziumschicht (69) und auf der freiliegenden Halbleiterschicht eine Siliziumeinkristall-Schicht (68) ausbildet, die (durch epitaxiales Aufwachsen) gebildete Schicht mit einem das polykristalline Silizium rascher als den Siliziumeinkristall (weg)ätzenden Ätzmittel ätzt, um einen aus dem Siliziumeinkristall (68) und dem angrenzenden Teil (69) des polykristallinen Siliziums bestehenden Vorsprung zu bilden, zur Bildung eines zweiten Halbleiterbereiches (70) in dem Vorsprung aus dem Siliziumeinkristall in diesen ein Fremdatom eines zweiten Leitfähigkeitstyps in niedriger Konzentration einführt, zur Bildung eines dritten Halbleiterbereiches (71) am oberen Teil des Vorsprungs aus dem Siliziumeinkristall in die Vorsprungoberfläche ein Fremdatom des ersten Leitfähigkeitstyps in hoher Konzentration einführt, auf dem Vorsprung eine dritte isolierende Schicht (72) ausbildet, die zweite isolierende Schicht (67) entfernt, zur Bildung eines vierten Halbleiterbereichs (70b) in den freiliegenden ersten Halbleiterbereich ein Fremdatom des zweiten Leitfähigkeitstyps in höherer Konzentration, als sie in dem zweiten Halbleiterbereich (70) herrscht, einführt, und eine Verbindungselektrode (74a, 74b, 74c) des gewünschten Musters ausbildet.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß man auf der zweiten isolierenden Schicht (47, 67) und dem freiliegenden zweiten Halbleiterbereich (46, 63) die polykristalline Siliziumschicht (49a, 69) bzw. die Siliziumeinkristallschicht (48, 68) durch epitaxiales Aufwachsen von Silizium ausbildet.
4. Verfahren nach Ansprüchen 1 und 3, dadurch gekennzeichnet, daß man die epitaxiales Aufwachsen eine undotierte Siliziumschicht erzeugt.
5. Verfahren nach Ansprüchen 1 und 3, dadurch gekennzeichnet, daß man durch epitaxiales Aufwachsen eine fremdatomdotierte Siliziumschicht erzeugt.
6. Verfahren nach Ansprüchen 1 und 3, dadurch gekennzeichnet, daß man zusätzlich in die durch epitaxiales Aufwachsen gebildete Schicht vor deren Ätzen ein Fremdatom des ersten Leitfähigkeitstyps einführt.
7. Verfahren nach Ansprüchen 1 und 3, dadurch gekennzeichnet, daß man zusätzlich in den zweiten Halbleiterbereich (46) nach Entfernen der zweiten isolierenden Schicht (47) ein Fremdatom des zweiten Leitfähigkeitstyps in hoher Konzentration einführt.
8. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß man die durch epitaxiales Aufwachsen gebildete Schicht unter solchen Bedingungen ätzt, daß eine ätzbeständige Maske die aneinander angrenzenden Bereiche des polykristallinen Siliziums und des Siliziumeinkristalls bedeckt.
9. Verfahren nach Anspruch 3, dadurch gekennzeichnet, daß man zum Ätzen der durch epitaxiales Aufwachsen gebildeten Schicht ein Gemisch aus HF, HN03 und CH3COOH, ein Gemisch aus HF, HN03, CH3COOH und H20 oder ein gasförmiges Ätzmittel mit einem Fluorkohlenstoff verwendet.
10. Verfahren nach Ansprüchen 2 und 3, dadurch gekennzeichnet, daß man zusätzlich auf der zweiten isolierenden Schicht (109) eine vierte isolierende Schicht (111) mit mindestens einer Öffnung und einem Fremdatomgehalt ausbildet, nach dem epitaxialen Aufwachsen eine Wärmebehandlung durchführt und das in der vierten isolierenden Schicht enthaltene Fremdatom zur selektiven Ausbildung eines fremdatomdotierten Bereiches (113b) in der polykristallinen Siliziumschicht in die polykristalline Siliziumschicht diffundieren läßt und schließlich nach dem (Weg)ätzen der durch epitaxiales Aufwachsen gebildeten Schicht die vierte isolierende Schicht entfernt, wobei die undotierte polykristalline Siliziumschicht (114a) auf der zweiten isolierenden Schicht (109) verbleibt.
11. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß man die polykristalline Siliziumschicht (49a, 69) und die Siliziumeinkristall-Schicht (48, 68) dadurch ausbildet, daß man auf der Oberfläche des Bauteils polykristallines oder amorphes Silizium ablagert und darauf Strahlungsenergie einwirken läßt, um auf der zweiten isolierenden Schicht (47, 67) eine polykristalline Siliziumschicht (49a, 69) und auf dem freiliegenden Halbleiterbereich (46, 63) eine Siliziumeinkristall-Schicht (48, 68) auszubilden.
12. Halbleitervorrichtung, gekennzeichnet durch eine Halbleiterschicht mit einem ersten Halbleiterbereich eines ersten Leitfähigkeitstyps, mindestens einen Vorsprung aus einer auf der Oberfläche der Halbleiterschicht gebildeten S-liziumeinkristall-Schicht (46a, 51) und einer daran angrenzenden polykristallinen Siliziumschicht, eine auf der Oberfläche des Vorsprungs gebildete isolierende Schicht (52), einem am unteren Teil der Siliziumeinkristall- Schicht gebildeten zweiten Halbleiterbereich (46a) eines zweiten Leitfähigkeitstyps, einen am oberen Teil der Siliziumeinkristall-Schicht gebildeten und mit dem zweiten Halbleiterbereich (46a) in Verbindung stehenden dritten Halbleiterbereich (51), einen vierten Halbleiterbereich (46b) höherer Fremdatomkonzentration, als sie der zweite Halbleiterbereich (46a) aufweist, und desselben Leitfähigkeitstyps wie der zweite Halbleiterbereich (46a), wobei der vierte Halbleiterbereich (46b) in dem ersten Halbleiterbereich an beiden Seiten des Vorsprungs derart ausgebildet ist, daß er mit dem zweiten Halbleiterbereich (46a) in Verbindung steht, und eine mit dem vierten Halbleiterbereich (46b) verbundene und von dem dritten Halbleiterbereich (51) durch die isolierende Schicht (52) isolierte Verbindungselektrode (54) (Fig. 10).
13. Halbeleitervorrichtung nach Anspruch 12, dadurch gekennzeichnet, daß die polykristalline Siliziumschicht als Elektrodenanschlußleiter für den dritten Halbleiterbereich dient.
EP19810101993 1980-03-22 1981-03-17 Halbleiterbauelement und Verfahren zu seiner Herstellung Expired EP0036620B1 (de)

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JP3577580A JPS56133864A (en) 1980-03-22 1980-03-22 Semiconductor device and manufacture thereof
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JP55182336A JPS57106067A (en) 1980-12-23 1980-12-23 Manufacture of semiconductor device
JP182336/80 1980-12-23

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GB8926414D0 (en) * 1989-11-18 1990-01-10 Lsi Logic Europ Bipolar junction transistors
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