EP0009678B1 - Ein-/Ausgabevorrichtung für Computer - Google Patents

Ein-/Ausgabevorrichtung für Computer Download PDF

Info

Publication number
EP0009678B1
EP0009678B1 EP79103408A EP79103408A EP0009678B1 EP 0009678 B1 EP0009678 B1 EP 0009678B1 EP 79103408 A EP79103408 A EP 79103408A EP 79103408 A EP79103408 A EP 79103408A EP 0009678 B1 EP0009678 B1 EP 0009678B1
Authority
EP
European Patent Office
Prior art keywords
signal
burst
programmed
input
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP79103408A
Other languages
English (en)
French (fr)
Other versions
EP0009678A1 (de
Inventor
Robert Lowell Adams Jr.
Carl Henry Grant
Karl Wayhe Stevens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0009678A1 publication Critical patent/EP0009678A1/de
Application granted granted Critical
Publication of EP0009678B1 publication Critical patent/EP0009678B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control

Definitions

  • the present invention relates to a computer input/output apparatus as indicated in the precharacterising part of claim 1.
  • Such apparatus is known from IBM Technical Disclosure Bulletin, vol. 17, no. 10, March 1975, pp. 2992 to 3001.
  • an I/0 program is executed within a computer going through the steps of addressing an I/0 device, sending a command to the addressed I/0 device to instruct the device to either send or receive data, and either receiving or sending several bytes of data to the I/O device.
  • the amount of data transferred during one I/O device selection is kept small so that the channel will be available without long delays for receiving interrupt requests from other transfer devices requiring service.
  • the data passes through the Central Processing Unit (CPU) and is stored in the memory by the CPU instruction.
  • CPU Central Processing Unit
  • Real time devices often use the programmed input/output data transfer method in order that the computer may have immediate access to the data being received. Immediate data access allows immediate response calculation for transmission to the real time device.
  • Nonreal time devices such as disk memories and tape drives can be more efficiently operated in what is sometimes termed "device initiated burst mode".
  • Device initiated data transfer is initiated by a signal such as cycle steal request being sent from a device to a computer which terminates instruction execution after completion of the currently executing instruction.
  • the computer Upon termination of instruction execution, the computer sends a cycle steal grant response to all I/O devices which are connected in a daisy chain sequence. If two devices require service simultaneously, both will raise a cycle steal request signal but the device with highest priority will receive the cycle steal grant signal first and can inhibit propagation to the lower priority device.
  • the disk control logic can place an identifying port address on the data bus, a command indicating whether the device which is to send or receive data and thereafter a single sequential burst of data bytes without intervening address and command information.
  • data does not pass through the CPU itself, but rather is passed directly to sequential memory addresses under control of an indexing address counter in the selected port of the input/output channel.
  • each port has a byte counter in the associated burst mode device containing the length of the data transfer. As each byte is transferred, the count is decremented. When the count reaches zero, the data transfer has been completed and the burst mode device generates an end of chain signal.
  • Each port address counter and byte counter are loaded by programmed instructions prior to the start of any burst data transfer. If the input/output channel is slower than memory, time slots may become available within which the computer can be given access to the memory without interfering with data being transferred by the channel.
  • the Central Processor Unit cannot execute a programmed I/0 operation to serve a real time device until the entire burst of data has been transmitted.
  • the burst of data may constitute a single block of 256 or 1,024 bytes requiring significant transmission time and leading to excessive response time for the real time device.
  • a partial solution to this problem is proposed in the prior art by permitting a higher priority device capable of device initiated data transfer to suspend transfer by a lower priority device in the middle of a burst and substitute its own port address, command and/or data sequence.
  • the lower priority device resumes the transmission of its burst upon completion of transmission by the high priority device.
  • the above described partial solution is incomplete because although a real time device can provide its data into memory, it has no way of receiving a response until all of the lower priority transmitting and suspended bursts have been completed. Until completed, the channel interface is not available for programmed input/output operations by the CPU. Furthermore, the CPU may be unaware of the existence of the real time data in memory since programmed I/O interruptions are inhibited during burst mode channel operations.
  • a computer 11, including a memory 13, a multiple interrupt level Central Processing Unit 15 and an integrated input/output channel 17 are shown connected to a common input/output bus 19.
  • Common bus 19 includes CS/PIO interface 21 and additional lines of the invention.
  • the interface 21 includes, for example, sixteen data wires and two parity wires for simultaneous parallel transmission of two bytes of data with parity.
  • Interface 21 will also include synchronizing tag lines. These tag lines indicate the content of data on the data wires to be an address, a command, or data and may, for example, be labelled TA, TC and TD.
  • TA indicates, for example that the information on the data wires is an address
  • TC and TD indicate that the information is a command or data.
  • Cycle steal request line 23 can be activated by any of the burst type devices which may also be a real time device.
  • Cycle steal request line 23 is an input to AND gate 101 which in turn sets the flip-flop 103.
  • Flip-flop 103 being set signals to integrated I/O channel 17 that a device initiated burst mode data transfer is being requested.
  • control of memory 13 is transferred to integrated I/O channel 17 and a cycle steal grant signal is propagated on line 25 through the I/0 devices in a prioritized daisy chain.
  • the burst mode output signal from flip-flop 103 is inverted by inverter 105 to remove the enable programmed I/O signal from the Central Processing Unit 15 thereby inhibiting CPU 15 from executing programmed I/O operations which would conflict with burst mode operations.
  • an instruction priority request signal can be generated by a real time device 51.
  • the instruction priority request signal is shown as being sent to computer 11 where it is amplified by amplifier 107 and sent to burst mode devices as a release signal on line 31. It will be recognized by those skilled in the art that the instruction priority request signal could have been sent directly to the burst mode devices without prior amplification by amplifier 107 in computer 11 so long as electrical drive capacities are not exceeded.
  • the instruction priority request signal is inverted by inverter 109 and applied to a second input of AND gate 101 to prevent flip-flop 103 from being set by burst mode devices after it becomes reset by a forced end of chain signal to be described hereafter.
  • a burst mode device 53 which may be in the midst of a data transfer burst will generate the forced end of chain signal on line 33 and terminate data transfer.
  • the forced end of chain signal resets latch 103 which in conjunction with inverter 105 enables programmed I/O operations by Central Processing Unit 15.
  • the real time device In conjunction with the return to programmed I/0 capability, the real time device would present its interrupt request on line 29 allowing interrupt level priority logic 111 to signal CPU 15 that programmed I/O service is required by real time device 51.
  • flip-flop 201 has a set input which is connected to an output of a real time event detector such as a voltage comparator, a relay, etc. signalling the need for real time processor intervention.
  • Flip-flop 201 being set provides the instruction priority request signal previously discussed with respect to the signals on wires 27 and 31.
  • the real time device also provides its interrupt request via flip-flop 203 to interrupt level priority logic 111.
  • the actual interrupt to CPU 15 will be presented to the internal interrupt circuits of CPU 15 when CPU 15 regains programmed I/O control of the input/output bus 19.
  • Each of flip-flops 201 and 203 are reset by programmed I/O commands from CPU 15 which are decoded by well-known command decode circuitry and applied to reset signal lines 205 and 207 respectively.
  • a buffer or other non-overrunable device By suspendable burst type device, a buffer or other non-overrunable device is to be considered.
  • a burst mode transfer of data is initiated by a condition such as buffer full during a read operation or buffer empty during a write operation.
  • the buffer full or buffer empty operation is recognized as a service request which sets latch 301.
  • Latch 301 being set causes AND gate 303 to propagate a cycle steal request signal onto line 23 of Fig. 1 because at this state active flip-flop 305 has not yet been set and accordingly inverter 307 satisfies the input conditions of AND gate 303.
  • a cycle steal grant signal will appear and set active flip-flop 305 via AND gate 309.
  • Inputs of AND gate 309 are connected to flip-flop 301, as well as the cycle steal grant input line. Because service request flip-flop 301 is set, inverter 311 1 having an output connected to AND gate 313 prevents propagation of the delayed cycle steal grant signal to the next lower priority device on bus 19.
  • the output of active flip-flop 305 is connected to inverter 307 as well as AND gates 315 and 317. Additionally, the output of active flip-flop 305 is connected to the reset inputs of flip-flops 323, 325 and 327.
  • AND gate 315 has an output connected to OR gate 329, which is in turn connected to AND gates 319, 331, and 333 as well as inverter 321.
  • AND gate 317 is likewise connected to OR gate 329.
  • the outputs of AND gates 315 and 317 are connected to control and data register gates not shown to transfer control information identifying the burst device channel port number to integrated I/O channel 17, while AND gate 317 transfers data between a buffer or non-overrunable I/O device and memory 13 at the data tag signal time TD.
  • Accompanying each data transfer will be a valid signal on the valid tag line generated by AND gate 333, which has inputs connected to service request flip-flop 301 as well as OR gate 329.
  • flip-flop 301 is reset while OR gate 335 is conditioned to provide an end of chain signal via AND gate 331.
  • the end of chain signal indicates to integrated I/O channel 17 that the burst data transfer has been completed.
  • Another input to OR gate 335 receives a signal from release flip-flop 325, which is in turn set by AND gate 319, which is in turn synchronized by flip-flop 323.
  • AND gate 337 has an input for receiving the release signal described earlier as being an amplified instruction priority request signal, which in combination with inverter 321 may set release synch flip-flop 323 between TD signals. The next TD signal sets flip-flop 325.
  • Release latch 325 being set allows AND gate 331 to generate an end of chain signal on line 33 even though normal end of message conditions have not been reached. Such a signal is referred to herein as a forced end of chain signal to distinguish it from a true end of chain signal signifying the actual completion of burst data transfer.
  • the forced end of chain signal resets latch 103 in computer 11 thereby terminating the burst mode operation and enabling programmed 1/0 operation.
  • the forced end of chain signal also is fed back to set latch 327, which allows AND gate 339 with inverter 341 to reset active flip-flop 305 as soon as the data transfer tag TD signal is removed. Active latch 305 being reset prevents AND gate 315, 317 from further data transmission thereby freeing the bus 19 for use by CPU 15.
  • CPU 15 Before burst mode operation can commence, CPU 15 must load the address counter and byte counter of each port to be used.
  • the address counters are loaded with the starting address of the blocks of memory in memory 13 which are to be involved in burst data transfers through each port.
  • a programmed I/O operation will load the channel port number and block size counter into a byte counter in each burst mode device.
  • a service request is generated internal to the burst mode device causing a cycle steal request for data transfer.
  • This cycle steal request sets burst mode latch 103 which results in integrated I/O channel 17 providing a cycle steal grant signal.
  • Integrated I/O channel 17 of Flg. 1 uses the port number to identify the address counter containing the memory addresses involved in the transfer. Thereafter a continuous sequence of TD data timing pulses, each associated with two bytes of data on the data wires of I/O bus 19.
  • Each TD signal control AND gate 317 of Fig. 3 to pass the data either into or out of burst device 53 and to increment the data counter.
  • the latches 201 and 203 in Fig. 2 are set by the real time event detected within the device.
  • Latches 201 and 203 generate instruction priority request and interrupt request signals respectively on lines 27 and 23 of bus 19.
  • the instruction priority request signal is inverted by inverter 109 to inhibit AND gate 101 and thereby prevent setting burst mode latch 103 if it has not already been set. In the event that it is already set, it will be reset by the forced end of chain signal from the burst transferring device.
  • instruction priority request (IPR) 401 is raised asynchronously when the real time device first requires service. Having raised the instruction priority request line, the release input via AND gate 337 sets release sync latch 323 at the end of the TD pulse. Latch 323 being set in turn causes release latch 325 to be set at the beginning of the next TD pulse. The output of release latch 325 forces an end of chain signal 403 via gates 335 and 331.
  • Burst data transfer is reestablished when the programmed I/O instruction resets flip-flop 201 thereby removing the instruction priority request signal 407 and allowing a cycle steal grant 409 to be generated by integrated I/O channel 17.
  • the cycle steal grant signal anded with the output of service register flip-flop 301 at AND gate 309 to again set active flip-flop 305.
  • Active flip-flop 305 being set in combination with the cycle steal grant input signal causes the control word 411 identifying the port being used to again be gated out on the data lines.
  • the control word is received by integrated I/O channel 17, it drops the signal on the cycle steal grant line and begins transmitting data timing pulses TD which are thereafter associated with each pair of data bytes 413 transferred.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Claims (3)

1. Ein- und Ausgabe-Steuereinheit eines Rechnersystems, die entweder im programmierten Ein- und Ausgabe-Betrieb, der von einer ersten Ein- und Ausgabeeinheit initiiert wird oder im Einpunktbetrieb, der von einer zweiten Ein- und Ausgabeeinheit initiiert wird, arbeitet, wobei die Ein und Ausgabesteuereinheit eine Unterbrechungsfolgeschaltung aufweist, die normalerweise dem Einpunkbetrieb die Priorität zuordnet, und die zweite Ein- und Ausgabeeinheit eine Schaltung zur Erzeugung eines Signals enthält, um das Suspendieren der Datenübertragung im Einpunktbetrieb anzuzeigen und weiterhin eine Schaltung enthält, die es ermöglicht, das die Einheit, die den Einpunkt-Datentransfer initiiert hat, diesen weiterführen kann, dadurch gekennzeichnet, daß in der ersten Einheit eine Schaltungsanordnung vorhanden ist, die ein programmiertes Instruktions-Prioritäts-Anforderungssignal erzeugt, wodurch dem Rechner Angezeigt wird, daß eine sofortige programmierte Ein- und Ausgabebedienung erforderlich ist und die die zweite Einheit anweist, die Einpunkt-Datenübertragung zu suspendieren, daß außerdem in der zweiten Einheit Schaltungen vorhanden sind, die ein erzwungenes Ende des Kettensignals erzeugen, um dem Rechner anzuzeigen, daß die Einpunkt-Datenübertragung suspendiert ist, daß im Rechner Schaltungsanordnungen vorhanden sind, die auf das erzwungene Ende des Kettensignals ansprechen, um die Einpunkt-Steuerung der Ein- und Ausgabesteuereinheit zu beenden, wodurch diese in dem programmierten Ein- und Ausgabe-Betrieb umgeschaltet wird, und daß Schaltungen vorhanden sind, die auf eine programmierte Ein- und Ausgabeinstruktion ansprechen, damit die Ein- und Ausgabeeinheit, die die Einpunkt-Datenübertragung initiiert hat, den Einpunktbetrieb wieder aufzunehmen kann.
2. Ein- und Ausgabesteuereinheit nach Anspruch 1, dadurch gekennzeichnet, daß der Rechner außerdem Schaltungen Enthält, die auf ein Instruktions-Prioritäts-Anforderungssignal ansprechen, um die Initiierung einer Einpunkt-Datenübertragung mit höherer Priorität zu verhindern.
3. Ein- und Ausgabesteuereinheit nach Anspruch 1, dadurch gekennzeichnet, daß die Schaltungen, die auf eine programmierte Ein-und Ausgabeinstruktion ansprechen, weitere Schaltungen in der ersten Ein- und Ausgabeinheit enthalten, die auf die programmierte Ein-und Ausgabeininstruktion ansprechen, um das Instruktions-Prioritäts-Anforderungssignal zu beenden, und daß im Rechner Schaltungen vorhanden sind, die auf das Beenden des Instruktionsprioritätssignals ansprechen, um ein Freigabesignal für die zweite Ein- und Ausgabeeinheit zu erzeugen, daß der zweiten Ein- und Ausgabeeinheit die Wiederaufnahme der Einpunkt-Datenübertragung ermöglicht.
EP79103408A 1978-10-02 1979-09-12 Ein-/Ausgabevorrichtung für Computer Expired EP0009678B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US948070 1978-10-02
US05/948,070 US4275440A (en) 1978-10-02 1978-10-02 I/O Interrupt sequencing for real time and burst mode devices

Publications (2)

Publication Number Publication Date
EP0009678A1 EP0009678A1 (de) 1980-04-16
EP0009678B1 true EP0009678B1 (de) 1982-12-08

Family

ID=25487213

Family Applications (1)

Application Number Title Priority Date Filing Date
EP79103408A Expired EP0009678B1 (de) 1978-10-02 1979-09-12 Ein-/Ausgabevorrichtung für Computer

Country Status (8)

Country Link
US (1) US4275440A (de)
EP (1) EP0009678B1 (de)
JP (1) JPS5847050B2 (de)
AU (1) AU531595B2 (de)
BR (1) BR7906341A (de)
CA (1) CA1115850A (de)
DE (1) DE2964214D1 (de)
ES (1) ES484505A1 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113162A (en) * 1980-12-29 1982-07-14 Fujitsu Ltd High-speed external storage device
US4558429A (en) * 1981-12-17 1985-12-10 Honeywell Information Systems Inc. Pause apparatus for a memory controller with interleaved queuing apparatus
US4611297A (en) * 1983-08-18 1986-09-09 Pitney Bowes Inc. Bus grant circuit
CA1266524A (en) * 1983-08-30 1990-03-06 Shinobu Arimoto Image processing system
US4636944A (en) * 1984-01-17 1987-01-13 Concurrent Computer Corporation Multi-level priority micro-interrupt controller
JPH0690700B2 (ja) * 1984-05-31 1994-11-14 富士通株式会社 半導体集積回路
US4713751A (en) * 1984-10-24 1987-12-15 International Business Machines Corporation Masking commands for a second processor when a first processor requires a flushing operation in a multiprocessor system
US4701845A (en) * 1984-10-25 1987-10-20 Unisys Corporation User interface processor for computer network with maintenance and programmable interrupt capability
US4779187A (en) * 1985-04-10 1988-10-18 Microsoft Corporation Method and operating system for executing programs in a multi-mode microprocessor
US4716523A (en) * 1985-06-14 1987-12-29 International Business Machines Corporation Multiple port integrated DMA and interrupt controller and arbitrator
US4837677A (en) * 1985-06-14 1989-06-06 International Business Machines Corporation Multiple port service expansion adapter for a communications controller
US4751634A (en) * 1985-06-14 1988-06-14 International Business Machines Corporation Multiple port communications adapter apparatus
US4779195A (en) * 1985-06-28 1988-10-18 Hewlett-Packard Company Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor
US4724520A (en) * 1985-07-01 1988-02-09 United Technologies Corporation Modular multiport data hub
US4719569A (en) * 1985-10-11 1988-01-12 Sun Microsystems, Inc. Arbitrator for allocating access to data processing resources
EP0288649B1 (de) * 1987-04-22 1992-10-21 International Business Machines Corporation Speichersteuersystem
WO1988008575A1 (en) * 1987-05-01 1988-11-03 Digital Equipment Corporation Interrupting node for providing interrupt requests to a pended bus
US4953072A (en) * 1987-05-01 1990-08-28 Digital Equipment Corporation Node for servicing interrupt request messages on a pended bus
JPH01258163A (ja) * 1988-04-08 1989-10-16 Fujitsu Ltd ダイレクトメモリアクセス制御装置
JPH01277928A (ja) * 1988-04-30 1989-11-08 Oki Electric Ind Co Ltd 印刷装置
US5029124A (en) * 1988-05-17 1991-07-02 Digital Equipment Corporation Method and apparatus for providing high speed parallel transfer of bursts of data
JPH05502526A (ja) * 1989-09-08 1993-04-28 オースペックス システムズ インコーポレイテッド 擬似同期ハンドシェイキングおよびブロックモードデータ転送を利用したエンハンストvmeバスプロトコル
US5379381A (en) * 1991-08-12 1995-01-03 Stratus Computer, Inc. System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
JP2519860B2 (ja) * 1991-09-16 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション バ―ストデ―タ転送装置および方法
US5319753A (en) * 1992-09-29 1994-06-07 Zilog, Inc. Queued interrupt mechanism with supplementary command/status/message information
CA2170380A1 (en) * 1993-02-11 1994-08-18 O.S. Mogdil Telemetry and control system
JPH0713772A (ja) * 1993-06-29 1995-01-17 Mitsubishi Electric Corp データ処理装置
DE69610450T2 (de) * 1995-03-13 2001-04-26 Sun Microsystems Inc Virtueller Ein/Ausgabeprozessor
KR100197646B1 (ko) * 1995-05-15 1999-06-15 김영환 버스트 모드 종료 검출장치
JP2792501B2 (ja) * 1996-02-28 1998-09-03 日本電気株式会社 データ転送方式およびデータ転送方法
FR2759177B1 (fr) * 1997-01-31 1999-04-23 Sextant Avionique Procede et dispositif de traitement de plusieurs applications techniques avec pour chacune d'elles la surete qui lui est propre
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US5978867A (en) 1997-08-21 1999-11-02 International Business Machines Corporation System for counting clock cycles stolen from a data processor and providing the count value to a second processor accessing the data processor cycle resources
US6058461A (en) * 1997-12-02 2000-05-02 Advanced Micro Devices, Inc. Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
US6434592B1 (en) * 1998-01-05 2002-08-13 Intel Corporation Method for accessing a network using programmed I/O in a paged, multi-tasking computer
US6438628B1 (en) * 1999-05-28 2002-08-20 3Com Corporation System and method for data pacing
US6708283B1 (en) 2000-04-13 2004-03-16 Stratus Technologies, Bermuda Ltd. System and method for operating a system with redundant peripheral bus controllers
US6735715B1 (en) 2000-04-13 2004-05-11 Stratus Technologies Bermuda Ltd. System and method for operating a SCSI bus with redundant SCSI adaptors
US6691257B1 (en) 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
US6633996B1 (en) 2000-04-13 2003-10-14 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus architecture
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6629178B1 (en) 2000-06-15 2003-09-30 Advanced Micro Devices, Inc. System and method for controlling bus access for bus agents having varying priorities
US6948010B2 (en) 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6766479B2 (en) 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations
US7065672B2 (en) 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6971043B2 (en) 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6996750B2 (en) * 2001-05-31 2006-02-07 Stratus Technologies Bermuda Ltd. Methods and apparatus for computer bus error termination
US7013357B2 (en) * 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Arbiter having programmable arbitration points for undefined length burst accesses and method
EP2567379A4 (de) * 2010-05-07 2014-01-22 Mosaid Technologies Inc Verfahren und vorrichtung zum gleichzeitigen lesen mehrerer speichervorrichtungen mithilfe eines einzelnen puffers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508206A (en) * 1967-05-01 1970-04-21 Control Data Corp Dimensioned interrupt
US3543242A (en) * 1967-07-07 1970-11-24 Ibm Multiple level priority system
US3543246A (en) * 1967-07-07 1970-11-24 Ibm Priority selector signalling device
US3705388A (en) * 1969-08-12 1972-12-05 Kogyo Gijutsuin Memory control system which enables access requests during block transfer
US3643229A (en) * 1969-11-26 1972-02-15 Stromberg Carlson Corp Interrupt arrangement for data processing systems
US3866181A (en) * 1972-12-26 1975-02-11 Honeywell Inf Systems Interrupt sequencing control apparatus
US3961312A (en) * 1974-07-15 1976-06-01 International Business Machines Corporation Cycle interleaving during burst mode operation
JPS5493934A (en) * 1978-01-06 1979-07-25 Hitachi Ltd Input/output control system

Also Published As

Publication number Publication date
AU4990679A (en) 1980-04-17
ES484505A1 (es) 1980-04-16
AU531595B2 (en) 1983-09-01
EP0009678A1 (de) 1980-04-16
JPS5549727A (en) 1980-04-10
US4275440A (en) 1981-06-23
JPS5847050B2 (ja) 1983-10-20
CA1115850A (en) 1982-01-05
DE2964214D1 (en) 1983-01-13
BR7906341A (pt) 1980-06-24

Similar Documents

Publication Publication Date Title
EP0009678B1 (de) Ein-/Ausgabevorrichtung für Computer
US4860244A (en) Buffer system for input/output portion of digital data processing system
EP0166272B1 (de) Buszugriff für Prozessor
US4096569A (en) Data processing system having distributed priority network with logic for deactivating information transfer requests
US4999769A (en) System with plural clocks for bidirectional information exchange between DMA controller and I/O devices via DMA bus
US4674033A (en) Multiprocessor system having a shared memory for enhanced interprocessor communication
EP0071782B1 (de) Mehrunterkanaladapter mit einem einzelnen Zustands-/Adressen-Register
US4669056A (en) Data processing system with a plurality of processors accessing a common bus to interleaved storage
US4041473A (en) Computer input/output control apparatus
EP0208430B1 (de) Verfahren und Gerät zur Durchführung von Datenleseoperationen mit veränderlicher Länge
US5572684A (en) IEEE 488 interface and message handling method
US5129072A (en) System for minimizing initiator processor interrupts by protocol controller in a computer bus system
US4365296A (en) System for controlling the duration of the time interval between blocks of data in a computer-to-computer communication system
US3961312A (en) Cycle interleaving during burst mode operation
EP0114523A2 (de) Verteiltes Prioritätslogiknetzwerk
US4719563A (en) Data transmission control device for controlling transfer of large amounts of data between two memory units
US5247640A (en) Dual access control system including plural magnetic disk control units and contention control circuitry
JP2581041B2 (ja) デ−タ処理装置
JP3442099B2 (ja) データ転送記憶装置
JP2848171B2 (ja) Scsiコントローラ
RU2018944C1 (ru) Устройство для сопряжения эвм с внешними объектами
JP2552025B2 (ja) データ転送方式
JPH07319841A (ja) シリアル制御装置
JPS6250848B2 (de)
JPS6161432B2 (de)

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): BE CH DE FR GB IT NL SE

17P Request for examination filed
ITF It: translation for a ep patent filed

Owner name: IBM - DR. ALFREDO BRAVI

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): BE CH DE FR GB IT NL SE

REF Corresponds to:

Ref document number: 2964214

Country of ref document: DE

Date of ref document: 19830113

ET Fr: translation filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 19840630

Year of fee payment: 6

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Effective date: 19890930

BERE Be: lapsed

Owner name: INTERNATIONAL BUSINESS MACHINES CORP.

Effective date: 19890930

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19900827

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19900828

Year of fee payment: 12

ITTA It: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19900930

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19901004

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19901218

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19910823

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19910913

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Effective date: 19910930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19920401

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19920529

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19920602

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19920912

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19920912

EUG Se: european patent has lapsed

Ref document number: 79103408.5

Effective date: 19920408

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT