EP0009678B1 - Ein-/Ausgabevorrichtung für Computer - Google Patents

Ein-/Ausgabevorrichtung für Computer Download PDF

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Publication number
EP0009678B1
EP0009678B1 EP79103408A EP79103408A EP0009678B1 EP 0009678 B1 EP0009678 B1 EP 0009678B1 EP 79103408 A EP79103408 A EP 79103408A EP 79103408 A EP79103408 A EP 79103408A EP 0009678 B1 EP0009678 B1 EP 0009678B1
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EP
European Patent Office
Prior art keywords
signal
burst
programmed
input
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP79103408A
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English (en)
French (fr)
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EP0009678A1 (de
Inventor
Robert Lowell Adams Jr.
Carl Henry Grant
Karl Wayhe Stevens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0009678A1 publication Critical patent/EP0009678A1/de
Application granted granted Critical
Publication of EP0009678B1 publication Critical patent/EP0009678B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control

Definitions

  • the present invention relates to a computer input/output apparatus as indicated in the precharacterising part of claim 1.
  • Such apparatus is known from IBM Technical Disclosure Bulletin, vol. 17, no. 10, March 1975, pp. 2992 to 3001.
  • an I/0 program is executed within a computer going through the steps of addressing an I/0 device, sending a command to the addressed I/0 device to instruct the device to either send or receive data, and either receiving or sending several bytes of data to the I/O device.
  • the amount of data transferred during one I/O device selection is kept small so that the channel will be available without long delays for receiving interrupt requests from other transfer devices requiring service.
  • the data passes through the Central Processing Unit (CPU) and is stored in the memory by the CPU instruction.
  • CPU Central Processing Unit
  • Real time devices often use the programmed input/output data transfer method in order that the computer may have immediate access to the data being received. Immediate data access allows immediate response calculation for transmission to the real time device.
  • Nonreal time devices such as disk memories and tape drives can be more efficiently operated in what is sometimes termed "device initiated burst mode".
  • Device initiated data transfer is initiated by a signal such as cycle steal request being sent from a device to a computer which terminates instruction execution after completion of the currently executing instruction.
  • the computer Upon termination of instruction execution, the computer sends a cycle steal grant response to all I/O devices which are connected in a daisy chain sequence. If two devices require service simultaneously, both will raise a cycle steal request signal but the device with highest priority will receive the cycle steal grant signal first and can inhibit propagation to the lower priority device.
  • the disk control logic can place an identifying port address on the data bus, a command indicating whether the device which is to send or receive data and thereafter a single sequential burst of data bytes without intervening address and command information.
  • data does not pass through the CPU itself, but rather is passed directly to sequential memory addresses under control of an indexing address counter in the selected port of the input/output channel.
  • each port has a byte counter in the associated burst mode device containing the length of the data transfer. As each byte is transferred, the count is decremented. When the count reaches zero, the data transfer has been completed and the burst mode device generates an end of chain signal.
  • Each port address counter and byte counter are loaded by programmed instructions prior to the start of any burst data transfer. If the input/output channel is slower than memory, time slots may become available within which the computer can be given access to the memory without interfering with data being transferred by the channel.
  • the Central Processor Unit cannot execute a programmed I/0 operation to serve a real time device until the entire burst of data has been transmitted.
  • the burst of data may constitute a single block of 256 or 1,024 bytes requiring significant transmission time and leading to excessive response time for the real time device.
  • a partial solution to this problem is proposed in the prior art by permitting a higher priority device capable of device initiated data transfer to suspend transfer by a lower priority device in the middle of a burst and substitute its own port address, command and/or data sequence.
  • the lower priority device resumes the transmission of its burst upon completion of transmission by the high priority device.
  • the above described partial solution is incomplete because although a real time device can provide its data into memory, it has no way of receiving a response until all of the lower priority transmitting and suspended bursts have been completed. Until completed, the channel interface is not available for programmed input/output operations by the CPU. Furthermore, the CPU may be unaware of the existence of the real time data in memory since programmed I/O interruptions are inhibited during burst mode channel operations.
  • a computer 11, including a memory 13, a multiple interrupt level Central Processing Unit 15 and an integrated input/output channel 17 are shown connected to a common input/output bus 19.
  • Common bus 19 includes CS/PIO interface 21 and additional lines of the invention.
  • the interface 21 includes, for example, sixteen data wires and two parity wires for simultaneous parallel transmission of two bytes of data with parity.
  • Interface 21 will also include synchronizing tag lines. These tag lines indicate the content of data on the data wires to be an address, a command, or data and may, for example, be labelled TA, TC and TD.
  • TA indicates, for example that the information on the data wires is an address
  • TC and TD indicate that the information is a command or data.
  • Cycle steal request line 23 can be activated by any of the burst type devices which may also be a real time device.
  • Cycle steal request line 23 is an input to AND gate 101 which in turn sets the flip-flop 103.
  • Flip-flop 103 being set signals to integrated I/O channel 17 that a device initiated burst mode data transfer is being requested.
  • control of memory 13 is transferred to integrated I/O channel 17 and a cycle steal grant signal is propagated on line 25 through the I/0 devices in a prioritized daisy chain.
  • the burst mode output signal from flip-flop 103 is inverted by inverter 105 to remove the enable programmed I/O signal from the Central Processing Unit 15 thereby inhibiting CPU 15 from executing programmed I/O operations which would conflict with burst mode operations.
  • an instruction priority request signal can be generated by a real time device 51.
  • the instruction priority request signal is shown as being sent to computer 11 where it is amplified by amplifier 107 and sent to burst mode devices as a release signal on line 31. It will be recognized by those skilled in the art that the instruction priority request signal could have been sent directly to the burst mode devices without prior amplification by amplifier 107 in computer 11 so long as electrical drive capacities are not exceeded.
  • the instruction priority request signal is inverted by inverter 109 and applied to a second input of AND gate 101 to prevent flip-flop 103 from being set by burst mode devices after it becomes reset by a forced end of chain signal to be described hereafter.
  • a burst mode device 53 which may be in the midst of a data transfer burst will generate the forced end of chain signal on line 33 and terminate data transfer.
  • the forced end of chain signal resets latch 103 which in conjunction with inverter 105 enables programmed I/O operations by Central Processing Unit 15.
  • the real time device In conjunction with the return to programmed I/0 capability, the real time device would present its interrupt request on line 29 allowing interrupt level priority logic 111 to signal CPU 15 that programmed I/O service is required by real time device 51.
  • flip-flop 201 has a set input which is connected to an output of a real time event detector such as a voltage comparator, a relay, etc. signalling the need for real time processor intervention.
  • Flip-flop 201 being set provides the instruction priority request signal previously discussed with respect to the signals on wires 27 and 31.
  • the real time device also provides its interrupt request via flip-flop 203 to interrupt level priority logic 111.
  • the actual interrupt to CPU 15 will be presented to the internal interrupt circuits of CPU 15 when CPU 15 regains programmed I/O control of the input/output bus 19.
  • Each of flip-flops 201 and 203 are reset by programmed I/O commands from CPU 15 which are decoded by well-known command decode circuitry and applied to reset signal lines 205 and 207 respectively.
  • a buffer or other non-overrunable device By suspendable burst type device, a buffer or other non-overrunable device is to be considered.
  • a burst mode transfer of data is initiated by a condition such as buffer full during a read operation or buffer empty during a write operation.
  • the buffer full or buffer empty operation is recognized as a service request which sets latch 301.
  • Latch 301 being set causes AND gate 303 to propagate a cycle steal request signal onto line 23 of Fig. 1 because at this state active flip-flop 305 has not yet been set and accordingly inverter 307 satisfies the input conditions of AND gate 303.
  • a cycle steal grant signal will appear and set active flip-flop 305 via AND gate 309.
  • Inputs of AND gate 309 are connected to flip-flop 301, as well as the cycle steal grant input line. Because service request flip-flop 301 is set, inverter 311 1 having an output connected to AND gate 313 prevents propagation of the delayed cycle steal grant signal to the next lower priority device on bus 19.
  • the output of active flip-flop 305 is connected to inverter 307 as well as AND gates 315 and 317. Additionally, the output of active flip-flop 305 is connected to the reset inputs of flip-flops 323, 325 and 327.
  • AND gate 315 has an output connected to OR gate 329, which is in turn connected to AND gates 319, 331, and 333 as well as inverter 321.
  • AND gate 317 is likewise connected to OR gate 329.
  • the outputs of AND gates 315 and 317 are connected to control and data register gates not shown to transfer control information identifying the burst device channel port number to integrated I/O channel 17, while AND gate 317 transfers data between a buffer or non-overrunable I/O device and memory 13 at the data tag signal time TD.
  • Accompanying each data transfer will be a valid signal on the valid tag line generated by AND gate 333, which has inputs connected to service request flip-flop 301 as well as OR gate 329.
  • flip-flop 301 is reset while OR gate 335 is conditioned to provide an end of chain signal via AND gate 331.
  • the end of chain signal indicates to integrated I/O channel 17 that the burst data transfer has been completed.
  • Another input to OR gate 335 receives a signal from release flip-flop 325, which is in turn set by AND gate 319, which is in turn synchronized by flip-flop 323.
  • AND gate 337 has an input for receiving the release signal described earlier as being an amplified instruction priority request signal, which in combination with inverter 321 may set release synch flip-flop 323 between TD signals. The next TD signal sets flip-flop 325.
  • Release latch 325 being set allows AND gate 331 to generate an end of chain signal on line 33 even though normal end of message conditions have not been reached. Such a signal is referred to herein as a forced end of chain signal to distinguish it from a true end of chain signal signifying the actual completion of burst data transfer.
  • the forced end of chain signal resets latch 103 in computer 11 thereby terminating the burst mode operation and enabling programmed 1/0 operation.
  • the forced end of chain signal also is fed back to set latch 327, which allows AND gate 339 with inverter 341 to reset active flip-flop 305 as soon as the data transfer tag TD signal is removed. Active latch 305 being reset prevents AND gate 315, 317 from further data transmission thereby freeing the bus 19 for use by CPU 15.
  • CPU 15 Before burst mode operation can commence, CPU 15 must load the address counter and byte counter of each port to be used.
  • the address counters are loaded with the starting address of the blocks of memory in memory 13 which are to be involved in burst data transfers through each port.
  • a programmed I/O operation will load the channel port number and block size counter into a byte counter in each burst mode device.
  • a service request is generated internal to the burst mode device causing a cycle steal request for data transfer.
  • This cycle steal request sets burst mode latch 103 which results in integrated I/O channel 17 providing a cycle steal grant signal.
  • Integrated I/O channel 17 of Flg. 1 uses the port number to identify the address counter containing the memory addresses involved in the transfer. Thereafter a continuous sequence of TD data timing pulses, each associated with two bytes of data on the data wires of I/O bus 19.
  • Each TD signal control AND gate 317 of Fig. 3 to pass the data either into or out of burst device 53 and to increment the data counter.
  • the latches 201 and 203 in Fig. 2 are set by the real time event detected within the device.
  • Latches 201 and 203 generate instruction priority request and interrupt request signals respectively on lines 27 and 23 of bus 19.
  • the instruction priority request signal is inverted by inverter 109 to inhibit AND gate 101 and thereby prevent setting burst mode latch 103 if it has not already been set. In the event that it is already set, it will be reset by the forced end of chain signal from the burst transferring device.
  • instruction priority request (IPR) 401 is raised asynchronously when the real time device first requires service. Having raised the instruction priority request line, the release input via AND gate 337 sets release sync latch 323 at the end of the TD pulse. Latch 323 being set in turn causes release latch 325 to be set at the beginning of the next TD pulse. The output of release latch 325 forces an end of chain signal 403 via gates 335 and 331.
  • Burst data transfer is reestablished when the programmed I/O instruction resets flip-flop 201 thereby removing the instruction priority request signal 407 and allowing a cycle steal grant 409 to be generated by integrated I/O channel 17.
  • the cycle steal grant signal anded with the output of service register flip-flop 301 at AND gate 309 to again set active flip-flop 305.
  • Active flip-flop 305 being set in combination with the cycle steal grant input signal causes the control word 411 identifying the port being used to again be gated out on the data lines.
  • the control word is received by integrated I/O channel 17, it drops the signal on the cycle steal grant line and begins transmitting data timing pulses TD which are thereafter associated with each pair of data bytes 413 transferred.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Claims (3)

1. Ein- und Ausgabe-Steuereinheit eines Rechnersystems, die entweder im programmierten Ein- und Ausgabe-Betrieb, der von einer ersten Ein- und Ausgabeeinheit initiiert wird oder im Einpunktbetrieb, der von einer zweiten Ein- und Ausgabeeinheit initiiert wird, arbeitet, wobei die Ein und Ausgabesteuereinheit eine Unterbrechungsfolgeschaltung aufweist, die normalerweise dem Einpunkbetrieb die Priorität zuordnet, und die zweite Ein- und Ausgabeeinheit eine Schaltung zur Erzeugung eines Signals enthält, um das Suspendieren der Datenübertragung im Einpunktbetrieb anzuzeigen und weiterhin eine Schaltung enthält, die es ermöglicht, das die Einheit, die den Einpunkt-Datentransfer initiiert hat, diesen weiterführen kann, dadurch gekennzeichnet, daß in der ersten Einheit eine Schaltungsanordnung vorhanden ist, die ein programmiertes Instruktions-Prioritäts-Anforderungssignal erzeugt, wodurch dem Rechner Angezeigt wird, daß eine sofortige programmierte Ein- und Ausgabebedienung erforderlich ist und die die zweite Einheit anweist, die Einpunkt-Datenübertragung zu suspendieren, daß außerdem in der zweiten Einheit Schaltungen vorhanden sind, die ein erzwungenes Ende des Kettensignals erzeugen, um dem Rechner anzuzeigen, daß die Einpunkt-Datenübertragung suspendiert ist, daß im Rechner Schaltungsanordnungen vorhanden sind, die auf das erzwungene Ende des Kettensignals ansprechen, um die Einpunkt-Steuerung der Ein- und Ausgabesteuereinheit zu beenden, wodurch diese in dem programmierten Ein- und Ausgabe-Betrieb umgeschaltet wird, und daß Schaltungen vorhanden sind, die auf eine programmierte Ein- und Ausgabeinstruktion ansprechen, damit die Ein- und Ausgabeeinheit, die die Einpunkt-Datenübertragung initiiert hat, den Einpunktbetrieb wieder aufzunehmen kann.
2. Ein- und Ausgabesteuereinheit nach Anspruch 1, dadurch gekennzeichnet, daß der Rechner außerdem Schaltungen Enthält, die auf ein Instruktions-Prioritäts-Anforderungssignal ansprechen, um die Initiierung einer Einpunkt-Datenübertragung mit höherer Priorität zu verhindern.
3. Ein- und Ausgabesteuereinheit nach Anspruch 1, dadurch gekennzeichnet, daß die Schaltungen, die auf eine programmierte Ein-und Ausgabeinstruktion ansprechen, weitere Schaltungen in der ersten Ein- und Ausgabeinheit enthalten, die auf die programmierte Ein-und Ausgabeininstruktion ansprechen, um das Instruktions-Prioritäts-Anforderungssignal zu beenden, und daß im Rechner Schaltungen vorhanden sind, die auf das Beenden des Instruktionsprioritätssignals ansprechen, um ein Freigabesignal für die zweite Ein- und Ausgabeeinheit zu erzeugen, daß der zweiten Ein- und Ausgabeeinheit die Wiederaufnahme der Einpunkt-Datenübertragung ermöglicht.
EP79103408A 1978-10-02 1979-09-12 Ein-/Ausgabevorrichtung für Computer Expired EP0009678B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/948,070 US4275440A (en) 1978-10-02 1978-10-02 I/O Interrupt sequencing for real time and burst mode devices
US948070 1978-10-02

Publications (2)

Publication Number Publication Date
EP0009678A1 EP0009678A1 (de) 1980-04-16
EP0009678B1 true EP0009678B1 (de) 1982-12-08

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EP79103408A Expired EP0009678B1 (de) 1978-10-02 1979-09-12 Ein-/Ausgabevorrichtung für Computer

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US (1) US4275440A (de)
EP (1) EP0009678B1 (de)
JP (1) JPS5847050B2 (de)
AU (1) AU531595B2 (de)
BR (1) BR7906341A (de)
CA (1) CA1115850A (de)
DE (1) DE2964214D1 (de)
ES (1) ES484505A1 (de)

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Also Published As

Publication number Publication date
JPS5847050B2 (ja) 1983-10-20
BR7906341A (pt) 1980-06-24
AU4990679A (en) 1980-04-17
US4275440A (en) 1981-06-23
JPS5549727A (en) 1980-04-10
AU531595B2 (en) 1983-09-01
EP0009678A1 (de) 1980-04-16
ES484505A1 (es) 1980-04-16
CA1115850A (en) 1982-01-05
DE2964214D1 (en) 1983-01-13

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