DE2964214D1 - Computer input/output apparatus - Google Patents

Computer input/output apparatus

Info

Publication number
DE2964214D1
DE2964214D1 DE7979103408T DE2964214T DE2964214D1 DE 2964214 D1 DE2964214 D1 DE 2964214D1 DE 7979103408 T DE7979103408 T DE 7979103408T DE 2964214 T DE2964214 T DE 2964214T DE 2964214 D1 DE2964214 D1 DE 2964214D1
Authority
DE
Germany
Prior art keywords
output apparatus
computer input
computer
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979103408T
Other languages
English (en)
Inventor
Jr Robert Lowell Adams
Carl Henry Grant
Karl Wayhe Stevens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2964214D1 publication Critical patent/DE2964214D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
DE7979103408T 1978-10-02 1979-09-12 Computer input/output apparatus Expired DE2964214D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/948,070 US4275440A (en) 1978-10-02 1978-10-02 I/O Interrupt sequencing for real time and burst mode devices

Publications (1)

Publication Number Publication Date
DE2964214D1 true DE2964214D1 (en) 1983-01-13

Family

ID=25487213

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979103408T Expired DE2964214D1 (en) 1978-10-02 1979-09-12 Computer input/output apparatus

Country Status (8)

Country Link
US (1) US4275440A (de)
EP (1) EP0009678B1 (de)
JP (1) JPS5847050B2 (de)
AU (1) AU531595B2 (de)
BR (1) BR7906341A (de)
CA (1) CA1115850A (de)
DE (1) DE2964214D1 (de)
ES (1) ES484505A1 (de)

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US4611297A (en) * 1983-08-18 1986-09-09 Pitney Bowes Inc. Bus grant circuit
FR2551236B1 (fr) * 1983-08-30 1990-07-06 Canon Kk Systeme de traitement d'image
US4636944A (en) * 1984-01-17 1987-01-13 Concurrent Computer Corporation Multi-level priority micro-interrupt controller
JPH0690700B2 (ja) * 1984-05-31 1994-11-14 富士通株式会社 半導体集積回路
US4713751A (en) * 1984-10-24 1987-12-15 International Business Machines Corporation Masking commands for a second processor when a first processor requires a flushing operation in a multiprocessor system
US4701845A (en) * 1984-10-25 1987-10-20 Unisys Corporation User interface processor for computer network with maintenance and programmable interrupt capability
US4779187A (en) * 1985-04-10 1988-10-18 Microsoft Corporation Method and operating system for executing programs in a multi-mode microprocessor
US4837677A (en) * 1985-06-14 1989-06-06 International Business Machines Corporation Multiple port service expansion adapter for a communications controller
US4751634A (en) * 1985-06-14 1988-06-14 International Business Machines Corporation Multiple port communications adapter apparatus
US4716523A (en) * 1985-06-14 1987-12-29 International Business Machines Corporation Multiple port integrated DMA and interrupt controller and arbitrator
US4779195A (en) * 1985-06-28 1988-10-18 Hewlett-Packard Company Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a particular processor
US4724520A (en) * 1985-07-01 1988-02-09 United Technologies Corporation Modular multiport data hub
US4719569A (en) * 1985-10-11 1988-01-12 Sun Microsystems, Inc. Arbitrator for allocating access to data processing resources
EP0288649B1 (de) * 1987-04-22 1992-10-21 International Business Machines Corporation Speichersteuersystem
US4953072A (en) * 1987-05-01 1990-08-28 Digital Equipment Corporation Node for servicing interrupt request messages on a pended bus
KR930002791B1 (ko) * 1987-05-01 1993-04-10 디지탈이큅먼트 코오포레이숀 펜디드 버스에서의 인터럽트 서비스노드
JPH01258163A (ja) * 1988-04-08 1989-10-16 Fujitsu Ltd ダイレクトメモリアクセス制御装置
JPH01277928A (ja) * 1988-04-30 1989-11-08 Oki Electric Ind Co Ltd 印刷装置
US5029124A (en) * 1988-05-17 1991-07-02 Digital Equipment Corporation Method and apparatus for providing high speed parallel transfer of bursts of data
EP0490988A4 (en) * 1989-09-08 1993-05-12 Auspex Systems, Inc. Enhanced vmebus protocol utilizing pseudosynchronous handshaking and block mode data transfer
US5379381A (en) * 1991-08-12 1995-01-03 Stratus Computer, Inc. System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations
JP2519860B2 (ja) * 1991-09-16 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション バ―ストデ―タ転送装置および方法
US5319753A (en) * 1992-09-29 1994-06-07 Zilog, Inc. Queued interrupt mechanism with supplementary command/status/message information
WO1994018803A1 (en) * 1993-02-11 1994-08-18 National Digital Electronics, Inc. Telemetry and control system
JPH0713772A (ja) * 1993-06-29 1995-01-17 Mitsubishi Electric Corp データ処理装置
DE69610450T2 (de) * 1995-03-13 2001-04-26 Sun Microsystems Inc Virtueller Ein/Ausgabeprozessor
KR100197646B1 (ko) * 1995-05-15 1999-06-15 김영환 버스트 모드 종료 검출장치
JP2792501B2 (ja) * 1996-02-28 1998-09-03 日本電気株式会社 データ転送方式およびデータ転送方法
FR2759177B1 (fr) * 1997-01-31 1999-04-23 Sextant Avionique Procede et dispositif de traitement de plusieurs applications techniques avec pour chacune d'elles la surete qui lui est propre
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US5978867A (en) * 1997-08-21 1999-11-02 International Business Machines Corporation System for counting clock cycles stolen from a data processor and providing the count value to a second processor accessing the data processor cycle resources
US6058461A (en) * 1997-12-02 2000-05-02 Advanced Micro Devices, Inc. Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
US6434592B1 (en) * 1998-01-05 2002-08-13 Intel Corporation Method for accessing a network using programmed I/O in a paged, multi-tasking computer
US6438628B1 (en) * 1999-05-28 2002-08-20 3Com Corporation System and method for data pacing
US6633996B1 (en) 2000-04-13 2003-10-14 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus architecture
US6691257B1 (en) 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
US6735715B1 (en) 2000-04-13 2004-05-11 Stratus Technologies Bermuda Ltd. System and method for operating a SCSI bus with redundant SCSI adaptors
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6708283B1 (en) 2000-04-13 2004-03-16 Stratus Technologies, Bermuda Ltd. System and method for operating a system with redundant peripheral bus controllers
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6629178B1 (en) 2000-06-15 2003-09-30 Advanced Micro Devices, Inc. System and method for controlling bus access for bus agents having varying priorities
US6948010B2 (en) 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6766479B2 (en) 2001-02-28 2004-07-20 Stratus Technologies Bermuda, Ltd. Apparatus and methods for identifying bus protocol violations
US7065672B2 (en) 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6971043B2 (en) 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6996750B2 (en) * 2001-05-31 2006-02-07 Stratus Technologies Bermuda Ltd. Methods and apparatus for computer bus error termination
US7013357B2 (en) * 2003-09-12 2006-03-14 Freescale Semiconductor, Inc. Arbiter having programmable arbitration points for undefined length burst accesses and method
TW201209820A (en) * 2010-05-07 2012-03-01 Mosaid Technologies Inc Method and apparatus for concurrently reading a plurality of memory devices using a single buffer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508206A (en) * 1967-05-01 1970-04-21 Control Data Corp Dimensioned interrupt
US3543242A (en) * 1967-07-07 1970-11-24 Ibm Multiple level priority system
US3543246A (en) * 1967-07-07 1970-11-24 Ibm Priority selector signalling device
US3705388A (en) * 1969-08-12 1972-12-05 Kogyo Gijutsuin Memory control system which enables access requests during block transfer
US3643229A (en) * 1969-11-26 1972-02-15 Stromberg Carlson Corp Interrupt arrangement for data processing systems
US3866181A (en) * 1972-12-26 1975-02-11 Honeywell Inf Systems Interrupt sequencing control apparatus
US3961312A (en) * 1974-07-15 1976-06-01 International Business Machines Corporation Cycle interleaving during burst mode operation
JPS5493934A (en) * 1978-01-06 1979-07-25 Hitachi Ltd Input/output control system

Also Published As

Publication number Publication date
AU4990679A (en) 1980-04-17
JPS5847050B2 (ja) 1983-10-20
JPS5549727A (en) 1980-04-10
EP0009678A1 (de) 1980-04-16
EP0009678B1 (de) 1982-12-08
BR7906341A (pt) 1980-06-24
AU531595B2 (en) 1983-09-01
CA1115850A (en) 1982-01-05
US4275440A (en) 1981-06-23
ES484505A1 (es) 1980-04-16

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee