EP0000480B1 - Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium - Google Patents

Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium Download PDF

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Publication number
EP0000480B1
EP0000480B1 EP78100268A EP78100268A EP0000480B1 EP 0000480 B1 EP0000480 B1 EP 0000480B1 EP 78100268 A EP78100268 A EP 78100268A EP 78100268 A EP78100268 A EP 78100268A EP 0000480 B1 EP0000480 B1 EP 0000480B1
Authority
EP
European Patent Office
Prior art keywords
silicon
silicon layer
semiconductor element
temperature
semiconductor elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100268A
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German (de)
English (en)
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EP0000480A1 (fr
Inventor
Jürgen Krausse
Wilhelm Ladenhauf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0000480A1 publication Critical patent/EP0000480A1/fr
Application granted granted Critical
Publication of EP0000480B1 publication Critical patent/EP0000480B1/fr
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Definitions

  • a major problem with semiconductor components is keeping the current-voltage characteristics stable.
  • rectifiers and transistors these are, in particular, the characteristic curves in the reverse direction, while in the case of thyristors attention should be paid to the stability of the characteristic curves in the reverse direction and in the tilt direction.
  • DE-B-1 185 896 describes a passivation method in which silicon is vapor-deposited on the surface of a semiconductor element in a high vacuum.
  • the evaporation can be carried out at comparatively lower temperatures than in the thermal decomposition of a silicon compound. This enables passivation of components that have already been contacted and assembled.
  • the invention accordingly relates to a method for passivating semiconductor components, in which a silicon layer is evaporated onto the surface of the semiconductor elements in a high vacuum.
  • the invention is therefore based on the object of developing this passivation method in such a way that low reverse currents can be achieved.
  • the invention is characterized in that the vapor-deposited silicon layer is annealed at such a temperature between the room temperature and the crystallization temperature of the vapor-deposited silicon that a desired reduction in the blocking currents is achieved.
  • the semiconductor element of a thyristor is shown in section. It has four zones, of which the cathode-side emitter zone is designated 1, the cathode-side base zone 2, the inner base zone 3 and the anode-side emitter zone 4. There are pn junctions 5, 6, 7 between the zones mentioned.
  • the semiconductor element consists of silicon and the zones mentioned are doped in a conventional manner depending on the intended use of the semiconductor component.
  • a protective layer 8 made of silicon is vapor-deposited onto the edge of the semiconductor element, at least at the points at which the pn junctions come to the surface, which can be, for example, 0.1 ⁇ m or thicker, for example 1 ⁇ m.
  • the areas of the semiconductor element that are not to be vaporized are covered before the vapor deposition.
  • a further protective layer 9 can be applied to the evaporated silicon layer 8, which can consist, for example, of normal rubber or another protective lacquer.
  • the evaporated silicon layer 8 can contain dopants such as boron or phosphorus to adjust the specific resistance. A content of the mentioned dopants is increased by evaporating one or more of these substances with the silicon.
  • the layer 8 can also contain one or more metals such as aluminum for setting the specific resistance. The metals can also be built into the silicon by vapor deposition. The potential relationships at the edge of the semiconductor element can be adjusted by changing the specific resistance of layer 8.
  • the layer 8 may be, for example doped with phosphorus and have a resistivity of 10 ohm cm a.
  • the silicon layer 8 was in a vacuum evaporation system at a pressure of about 6.5. 10- 4 Pa (5. 10-6 Torr) by vapor deposition.
  • a silicon block can be used as the silicon source.
  • the silicon can be evaporated using an electron beam. With an acceleration voltage of 8 kV and a current of around 0.5 A, a vapor deposition rate of 0.25 ⁇ m / min was achieved. It can also be increased, for example, to 0.5 .mu.m / min and above by increasing the energy of the electron beam.
  • the silicon can also be evaporated by an ion beam, by direct current flow or by inductive heating. It it is also possible to evaporate the silicon by radiant heat.
  • the layer 8 can also consist of several successively vapor-deposited layers, each with different properties. A change in the specific resistance via the thickness and an influence on the potential relationships on the edge surface of the semiconductor element are thus obtained.
  • the evaporated silicon layer is annealed.
  • the annealing takes place at a temperature between room temperature and the crystallization temperature of the silicon.
  • the crystallization temperature of the silicon is between 427-627 ° C (700 and 900 ° K).
  • the annealing is carried out at a temperature which is below the melting temperature of the material used for contacting, for example soft solder, or another metallization.
  • the reverse current in the reverse direction and the reverse current in the tilting direction of the semiconductor element can be drastically reduced by the annealing.
  • FIG. 2 shows that the blocking current Isp for a certain type of semiconductor without the annealing at 2.
  • Evaporation of the silicon itself can be carried out at room temperature.
  • the temperature of the subsequent heat treatment can then be selected so that the desired reduction in the blocking currents is achieved without, for example, components which have already been contacted being affected. This makes it possible to passivate chips that have already been soldered and contacted, so that no masking or selective etching of the chips is required.
  • FIG. 3 in which the shape of the space charge zone is shown when the pn junction 7 is stressed in the reverse direction.
  • the boundaries 11, 12 of the space charge zone 10 run parallel to the pn junctions, for example. If there is a blocking load for a long time, the space charge zone widens in that the boundary 12 of the space charge zone 10 at the edge of the semiconductor element shifts in the direction of the pn junction 6. At the same time, the boundary 11 of the space charge zone 10 moves away from the pn junction 7, but only to a much weaker extent, since the zone 4 is more heavily doped than the zone 3.
  • the expansion of the space charge zone is shown in dashed lines in the figure.
  • the reverse current increases until the so-called punch-through effect occurs at the edge when the pn junction 6 is reached, where the pn junction 7 loses its blocking ability.
  • the widening also takes place at the pn junction 6 when the semiconductor element is loaded with a voltage in the reverse direction, that is to say the tilting direction.
  • the space charge zone 10 no longer widens at the edge. This can be determined, for example, using the known photoelectric method for examining the space charge zones at the edge of a semiconductor element. This means that the reverse currents do not increase, in other words that the characteristic curves remain stable in the reverse direction.
  • the invention has been described in connection with a semiconductor element for a thyristor. However, it can also be used in diodes, transistors and other semiconductor components. It can be used equally for mesa or planar structures. It is essential that silicon is evaporated onto at least the area in which the pn junctions appear on the surface of the half-meter element.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Claims (3)

1. Procédé pour passiver des composants à semiconducteurs, selon lequel on dépose par évaporation sous vide poussé une couche de silicium (8) à la surface des éléments semiconducteurs, caractérisé par le fait que la couche de silicium (8) déposé par évaporation est soumise à une recuit à une température située entre la température ambiante et la température de cristallistion du silicium déposé par évaporation et qui est telle que l'on obtient une réduction souhaitée des courants inverses.
2. Procédé selon la revendication 1, caractérisé par le fait que la couche (8) est soumise à un recuit à des températures qui sont inférieures à la température de fusion d'une métallisation déposée sur l'élément semiconducteur.
3. Procédé selon la revendication 1 ou 2, caractérisé par le fait qu'on effectue le recruit dans une atmosphère contenant de l'oxygène.
EP78100268A 1977-07-05 1978-06-28 Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium Expired EP0000480B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19772730367 DE2730367A1 (de) 1977-07-05 1977-07-05 Verfahren zum passivieren von halbleiterelementen
DE2730367 1977-07-05

Publications (2)

Publication Number Publication Date
EP0000480A1 EP0000480A1 (fr) 1979-02-07
EP0000480B1 true EP0000480B1 (fr) 1981-08-12

Family

ID=6013203

Family Applications (1)

Application Number Title Priority Date Filing Date
EP78100268A Expired EP0000480B1 (fr) 1977-07-05 1978-06-28 Procédé pour passiver des éléments semiconducteurs par application d'une couche de silicium

Country Status (7)

Country Link
US (1) US4322452A (fr)
EP (1) EP0000480B1 (fr)
JP (1) JPS5417672A (fr)
CA (1) CA1111149A (fr)
DE (1) DE2730367A1 (fr)
GB (1) GB1587030A (fr)
IT (1) IT1096857B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3021175A1 (de) * 1980-06-04 1981-12-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum passivieren von siliciumbauelementen
AT380974B (de) * 1982-04-06 1986-08-11 Shell Austria Verfahren zum gettern von halbleiterbauelementen
AT384121B (de) * 1983-03-28 1987-10-12 Shell Austria Verfahren zum gettern von halbleiterbauelementen
US4860066A (en) * 1987-01-08 1989-08-22 International Business Machines Corporation Semiconductor electro-optical conversion
ES2072321T3 (es) * 1989-02-01 1995-07-16 Siemens Ag Capa de pasivado electroactiva.
EP0381110B1 (fr) * 1989-02-01 1994-06-29 Siemens Aktiengesellschaft Couche de protection pour couches de passivation électroactives
US5213670A (en) * 1989-06-30 1993-05-25 Siemens Aktiengesellschaft Method for manufacturing a polycrystalline layer on a substrate
JP2501641B2 (ja) * 1989-07-19 1996-05-29 住友重機械工業株式会社 長尺搬送材の横送り装置
US5451550A (en) * 1991-02-20 1995-09-19 Texas Instruments Incorporated Method of laser CVD seal a die edge
DE4137341C1 (fr) * 1991-11-13 1993-04-29 Siemens Ag, 8000 Muenchen, De
US6885522B1 (en) 1999-05-28 2005-04-26 Fujitsu Limited Head assembly having integrated circuit chip covered by layer which prevents foreign particle generation
DE10358985B3 (de) * 2003-12-16 2005-05-19 Infineon Technologies Ag Halbleiterbauelement mit einem pn-Übergang und einer auf einer Oberfläche aufgebrachten Passivierungsschicht
US10581082B2 (en) * 2016-11-15 2020-03-03 Nanocomp Technologies, Inc. Systems and methods for making structures defined by CNT pulp networks

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2789258A (en) * 1955-06-29 1957-04-16 Raytheon Mfg Co Intrinsic coatings for semiconductor junctions
SE300472B (fr) * 1965-03-31 1968-04-29 Asea Ab
DE2018517B2 (de) * 1970-04-17 1973-02-22 Hitachi, Ltd , Tokio Erfahren zum herstellen eines halbleiterbauelements
US3765940A (en) * 1971-11-08 1973-10-16 Texas Instruments Inc Vacuum evaporated thin film resistors
US3806361A (en) * 1972-01-24 1974-04-23 Motorola Inc Method of making electrical contacts for and passivating a semiconductor device
JPS532552B2 (fr) * 1974-03-30 1978-01-28
JPS6022497B2 (ja) * 1974-10-26 1985-06-03 ソニー株式会社 半導体装置
JPS6041458B2 (ja) * 1975-04-21 1985-09-17 ソニー株式会社 半導体装置の製造方法
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit
FR2335951A1 (fr) * 1975-12-19 1977-07-15 Radiotechnique Compelec Dispositif semiconducteur a surface passivee et procede d'obtention de la structure de passivation
DE2632647A1 (de) * 1976-07-20 1978-01-26 Siemens Ag Halbleiterbauelement mit passivierender schutzschicht
DE2642413A1 (de) * 1976-09-21 1978-03-23 Siemens Ag Verfahren zum aufbringen einer aus silicium bestehenden passivierungsschicht
US4179528A (en) * 1977-05-18 1979-12-18 Eastman Kodak Company Method of making silicon device with uniformly thick polysilicon
US4134125A (en) * 1977-07-20 1979-01-09 Bell Telephone Laboratories, Incorporated Passivation of metallized semiconductor substrates

Also Published As

Publication number Publication date
JPS6158976B2 (fr) 1986-12-13
DE2730367C2 (fr) 1988-01-14
IT7825181A0 (it) 1978-06-30
GB1587030A (en) 1981-03-25
IT1096857B (it) 1985-08-26
CA1111149A (fr) 1981-10-20
JPS5417672A (en) 1979-02-09
EP0000480A1 (fr) 1979-02-07
DE2730367A1 (de) 1979-01-18
US4322452A (en) 1982-03-30

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