EP0000316A1 - Verfahren zur Herstellung von mit vertieften Siliziumoxidbereichen versehenen Halbleiteranordnungen - Google Patents

Verfahren zur Herstellung von mit vertieften Siliziumoxidbereichen versehenen Halbleiteranordnungen Download PDF

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Publication number
EP0000316A1
EP0000316A1 EP78430001A EP78430001A EP0000316A1 EP 0000316 A1 EP0000316 A1 EP 0000316A1 EP 78430001 A EP78430001 A EP 78430001A EP 78430001 A EP78430001 A EP 78430001A EP 0000316 A1 EP0000316 A1 EP 0000316A1
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EP
European Patent Office
Prior art keywords
substrate
silicon
mask
ions
oxidation
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Granted
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EP78430001A
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English (en)
French (fr)
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EP0000316B1 (de
Inventor
Billy Lee Crowder
William Ralph Hunter
Jr. Douglas William Ormond
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/966—Selective oxidation of ion-amorphousized layer

Definitions

  • the present invention relates to the manufacture of semiconductor devices comprising embedded oxide regions and more particularly to a method of direct application of a nitride mask on a substrate, typically of silicon, previously damaged by a step of ion implantation followed by annealing.
  • US Patent No. 3,961,999 describes a method for reducing the problems posed by the appearance of bird beaks.
  • the layer of silicon dioxide is conventionally located between the silicon substrate and the layer of silicon nitride.
  • This patent specifies that holes are first made by pickling in the silicon dioxide; these holes correspond to the openings previously made in the nitride mask but have a larger opening diameter.
  • the silicon in the substrate is eliminated in the holes.
  • a layer of silicon is therefore deposited overall over the entire structure, then the latter is oxidized.
  • the recessed dielectric isolation regions are relatively flat, but the problems posed by the presence of bird beaks are not fully resolved.
  • U.S. Patent No. 3,900,350 describes a solution to reduce bird beaks by using a layer of polycrystalline silicon under the oxidation mask in place of the usual silicon oxide.
  • this patent highlights the defects created by the stresses, which appear when the silicon nitride oxidation mask is placed directly on the silicon substrate.
  • the method of the present invention is interesting in that it eliminates the need for an intermediate layer, between the nitride mask and the substrate, which had the consequence of developing these bird beaks.
  • the process of the present invention allows the nitride mask to be deposited directly on the silicon substrate while eliminating the stress defects which usually appear with this practice.
  • the method of the present invention essentially comprises the step of initial damage to the surface of the silicon substrate by ion implantation to a controlled depth, then preferably followed by an annealing step to create a dense network of dislocations which prevent propagation of stress induced defects from the layer masking when proceeding to the step of depositing a mask against oxidation typically in silicon nitride directly on the surface of said substrate.
  • FIGS. 1A, 1B and 1C represent different stages of the manufacture of an oxide region embedded in a typically silicon semiconductor substrate using a mask for the composite oxidation: nitride-silicon dioxide, as it is usually carried out in the prior art.
  • FIGS. 2A, 2B, 2C and 2D illustrate different stages of the fabrication of an oxide region embedded in a semiconductor substrate typically of silicon using a mask for nitride oxidation, placed directly on the substrate, after the latter has undergone the steps of ion implantation and annealing in accordance with the principles of the present invention.
  • FIG. 1A a silicon substrate 10 and an oxidation mask 14 made of silicon nitride deposited on the desired region are shown.
  • the silicon nitride mask 14 is separated from the substrate 10 by a layer 12 of silicon dioxide, since, as we have seen, placing the nitride mask 14 directly on the substrate 10 would cause stress deformations in this substrate and would lead thus to poorly performing devices.
  • the embedded oxide 16 is obtained by thermal growth in the desired unmasked region and a projection 16 ′ appears under the mask 14.
  • the mask 14 is removed as shown in the Figure 1C. Because of this relatively wide projection of 16 'silicon oxide, along the recessed oxide configuration, a portion that resembles a bird's beak remains after removal of the nitride mask 14 and the layer d 'underlying thin oxide 12, by an appropriate pickling process.
  • This beak-shaped portion produces an unwanted masking effect during diffusion processes and can even determine the lateral border of the scattered area, in which case the pn junction formed between the scattered area and the substrate may have curved edges. In subsequent manufacturing steps, during the fabrication of the diffused area it is even possible that the pn junction may be exposed on the surface of the substrate.
  • a polycrystalline silicon layer may be used in place of the silicon dioxide layer.
  • This polycrystalline silicon layer placed on the monocrystalline silicon substrate reduces the stresses due to the nitride mask and at the same time reduces the projection in the shape of a bird's beak.
  • this technique thus uses a relatively thick intermediate layer which must be removed either directly or indirectly after conversion to oxide, by a pickling step.
  • FIG. 2A represents, in section, a silicon substrate 10 which has been subjected to an ion beam to a controlled depth d.
  • the ion implantation produces a very damaged layer 20 practically of amorphous silicon on the surface of the substrate 10.
  • the substrate 10 is then annealed and the heavily damaged layer 20 generates a very dense dislocation network, the microstructure of which depends on energy, the dose and the nature of the ions used during the implantation operation.
  • the dense dislocation network obtained after the implantation and annealing steps protects the mono silicon underlying lens of the defects induced by. constraints and allows the nitride oxidation mask 14 to be placed directly on the substrate 10 as illustrated in FIG. 2B.
  • FIG. 2C illustrates the structure after the oxidation step
  • FIG. 2D illustrates the structure after the elimination of the nitride oxidation mask and (if necessary) from the dense dislocation network 20, region in which no did not form a bird beak.
  • step (A) it is possible to carry out step (A) after step (B) provided that the ionic energy is large enough to perform the implantation operation through the nitride layer.
  • the choice of ions is mainly determined by the fact that in most cases they should not react electrically with silicon. For example, Si, Ge, Ar, Ne and O are possible bodies.
  • the energy of the implantation controls the depth of the damaged region.
  • the dose of ions must be close to the critical dose for a continuous amorphous layer to be effectively formed in the silicon, for example a dose of between 5 ⁇ 10 and 10 ⁇ 10 ions per cm 2 (for argon in silicon) is suitable.
  • step (F) may not be necessary in the manufacture of bipolar devices but may be necessary in the manufacture of MOS type field effect transistors.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
EP78430001A 1977-06-03 1978-06-01 Verfahren zur Herstellung von mit vertieften Siliziumoxidbereichen versehenen Halbleiteranordnungen Expired EP0000316B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/803,182 US4098618A (en) 1977-06-03 1977-06-03 Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation
US803182 1977-06-03

Publications (2)

Publication Number Publication Date
EP0000316A1 true EP0000316A1 (de) 1979-01-10
EP0000316B1 EP0000316B1 (de) 1981-04-29

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EP78430001A Expired EP0000316B1 (de) 1977-06-03 1978-06-01 Verfahren zur Herstellung von mit vertieften Siliziumoxidbereichen versehenen Halbleiteranordnungen

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US (1) US4098618A (de)
EP (1) EP0000316B1 (de)
JP (1) JPS542671A (de)
CA (1) CA1088217A (de)
DE (1) DE2860635D1 (de)
IT (1) IT1158723B (de)

Cited By (1)

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US20160185941A1 (en) * 2013-09-18 2016-06-30 Zeon Corporation Vinyl chloride resin composition for powder molding, and vinyl chloride resin molded body and laminate

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US4249962A (en) * 1979-09-11 1981-02-10 Western Electric Company, Inc. Method of removing contaminating impurities from device areas in a semiconductor wafer
JPS5650532A (en) * 1979-10-01 1981-05-07 Hitachi Ltd Manufacture of semiconductor device
JPS5734365A (en) * 1980-08-08 1982-02-24 Ibm Symmetrical bipolar transistor
DE3031170A1 (de) * 1980-08-18 1982-03-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-schaltungen nach dem sogenannten locos-verfahren
JPS57164547A (en) * 1981-04-02 1982-10-09 Toshiba Corp Manufacture of semiconductor device
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
JPS58114442A (ja) * 1981-12-26 1983-07-07 Fujitsu Ltd 半導体装置の製造方法
US4748134A (en) * 1987-05-26 1988-05-31 Motorola, Inc. Isolation process for semiconductor devices
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US5310457A (en) * 1992-09-30 1994-05-10 At&T Bell Laboratories Method of integrated circuit fabrication including selective etching of silicon and silicon compounds
US5330920A (en) * 1993-06-15 1994-07-19 Digital Equipment Corporation Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5869385A (en) * 1995-12-08 1999-02-09 Advanced Micro Devices, Inc. Selectively oxidized field oxide region
US5937310A (en) * 1996-04-29 1999-08-10 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
US5882993A (en) 1996-08-19 1999-03-16 Advanced Micro Devices, Inc. Integrated circuit with differing gate oxide thickness and process for making same
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
KR100211547B1 (ko) * 1996-10-29 1999-08-02 김영환 반도체 소자의 필드 산화막 형성방법
US5872376A (en) * 1997-03-06 1999-02-16 Advanced Micro Devices, Inc. Oxide formation technique using thin film silicon deposition
US6025240A (en) * 1997-12-18 2000-02-15 Advanced Micro Devices, Inc. Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
US6015736A (en) * 1997-12-19 2000-01-18 Advanced Micro Devices, Inc. Method and system for gate stack reoxidation control
TW358236B (en) * 1997-12-19 1999-05-11 Nanya Technology Corp Improved local silicon oxidization method in the manufacture of semiconductor isolation
US6258693B1 (en) 1997-12-23 2001-07-10 Integrated Device Technology, Inc. Ion implantation for scalability of isolation in an integrated circuit
US5962914A (en) * 1998-01-14 1999-10-05 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
US5998277A (en) * 1998-03-13 1999-12-07 Texas Instruments - Acer Incorporated Method to form global planarized shallow trench isolation
US6531364B1 (en) 1998-08-05 2003-03-11 Advanced Micro Devices, Inc. Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer
JP3732472B2 (ja) * 2002-10-07 2006-01-05 沖電気工業株式会社 Ｍｏｓトランジスタの製造方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160185941A1 (en) * 2013-09-18 2016-06-30 Zeon Corporation Vinyl chloride resin composition for powder molding, and vinyl chloride resin molded body and laminate

Also Published As

Publication number Publication date
CA1088217A (en) 1980-10-21
EP0000316B1 (de) 1981-04-29
JPS6141139B2 (de) 1986-09-12
JPS542671A (en) 1979-01-10
IT7823833A0 (it) 1978-05-26
DE2860635D1 (en) 1981-08-06
IT1158723B (it) 1987-02-25
US4098618A (en) 1978-07-04

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