EP0000316A1 - Method of manufacturing semiconductor devices comprising recessed silicon oxide regions - Google Patents

Method of manufacturing semiconductor devices comprising recessed silicon oxide regions Download PDF

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Publication number
EP0000316A1
EP0000316A1 EP78430001A EP78430001A EP0000316A1 EP 0000316 A1 EP0000316 A1 EP 0000316A1 EP 78430001 A EP78430001 A EP 78430001A EP 78430001 A EP78430001 A EP 78430001A EP 0000316 A1 EP0000316 A1 EP 0000316A1
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Prior art keywords
substrate
silicon
mask
ions
oxidation
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German (de)
French (fr)
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EP0000316B1 (en
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Billy Lee Crowder
William Ralph Hunter
Jr. Douglas William Ormond
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/966—Selective oxidation of ion-amorphousized layer

Definitions

  • the present invention relates to the manufacture of semiconductor devices comprising embedded oxide regions and more particularly to a method of direct application of a nitride mask on a substrate, typically of silicon, previously damaged by a step of ion implantation followed by annealing.
  • US Patent No. 3,961,999 describes a method for reducing the problems posed by the appearance of bird beaks.
  • the layer of silicon dioxide is conventionally located between the silicon substrate and the layer of silicon nitride.
  • This patent specifies that holes are first made by pickling in the silicon dioxide; these holes correspond to the openings previously made in the nitride mask but have a larger opening diameter.
  • the silicon in the substrate is eliminated in the holes.
  • a layer of silicon is therefore deposited overall over the entire structure, then the latter is oxidized.
  • the recessed dielectric isolation regions are relatively flat, but the problems posed by the presence of bird beaks are not fully resolved.
  • U.S. Patent No. 3,900,350 describes a solution to reduce bird beaks by using a layer of polycrystalline silicon under the oxidation mask in place of the usual silicon oxide.
  • this patent highlights the defects created by the stresses, which appear when the silicon nitride oxidation mask is placed directly on the silicon substrate.
  • the method of the present invention is interesting in that it eliminates the need for an intermediate layer, between the nitride mask and the substrate, which had the consequence of developing these bird beaks.
  • the process of the present invention allows the nitride mask to be deposited directly on the silicon substrate while eliminating the stress defects which usually appear with this practice.
  • the method of the present invention essentially comprises the step of initial damage to the surface of the silicon substrate by ion implantation to a controlled depth, then preferably followed by an annealing step to create a dense network of dislocations which prevent propagation of stress induced defects from the layer masking when proceeding to the step of depositing a mask against oxidation typically in silicon nitride directly on the surface of said substrate.
  • FIGS. 1A, 1B and 1C represent different stages of the manufacture of an oxide region embedded in a typically silicon semiconductor substrate using a mask for the composite oxidation: nitride-silicon dioxide, as it is usually carried out in the prior art.
  • FIGS. 2A, 2B, 2C and 2D illustrate different stages of the fabrication of an oxide region embedded in a semiconductor substrate typically of silicon using a mask for nitride oxidation, placed directly on the substrate, after the latter has undergone the steps of ion implantation and annealing in accordance with the principles of the present invention.
  • FIG. 1A a silicon substrate 10 and an oxidation mask 14 made of silicon nitride deposited on the desired region are shown.
  • the silicon nitride mask 14 is separated from the substrate 10 by a layer 12 of silicon dioxide, since, as we have seen, placing the nitride mask 14 directly on the substrate 10 would cause stress deformations in this substrate and would lead thus to poorly performing devices.
  • the embedded oxide 16 is obtained by thermal growth in the desired unmasked region and a projection 16 ′ appears under the mask 14.
  • the mask 14 is removed as shown in the Figure 1C. Because of this relatively wide projection of 16 'silicon oxide, along the recessed oxide configuration, a portion that resembles a bird's beak remains after removal of the nitride mask 14 and the layer d 'underlying thin oxide 12, by an appropriate pickling process.
  • This beak-shaped portion produces an unwanted masking effect during diffusion processes and can even determine the lateral border of the scattered area, in which case the pn junction formed between the scattered area and the substrate may have curved edges. In subsequent manufacturing steps, during the fabrication of the diffused area it is even possible that the pn junction may be exposed on the surface of the substrate.
  • a polycrystalline silicon layer may be used in place of the silicon dioxide layer.
  • This polycrystalline silicon layer placed on the monocrystalline silicon substrate reduces the stresses due to the nitride mask and at the same time reduces the projection in the shape of a bird's beak.
  • this technique thus uses a relatively thick intermediate layer which must be removed either directly or indirectly after conversion to oxide, by a pickling step.
  • FIG. 2A represents, in section, a silicon substrate 10 which has been subjected to an ion beam to a controlled depth d.
  • the ion implantation produces a very damaged layer 20 practically of amorphous silicon on the surface of the substrate 10.
  • the substrate 10 is then annealed and the heavily damaged layer 20 generates a very dense dislocation network, the microstructure of which depends on energy, the dose and the nature of the ions used during the implantation operation.
  • the dense dislocation network obtained after the implantation and annealing steps protects the mono silicon underlying lens of the defects induced by. constraints and allows the nitride oxidation mask 14 to be placed directly on the substrate 10 as illustrated in FIG. 2B.
  • FIG. 2C illustrates the structure after the oxidation step
  • FIG. 2D illustrates the structure after the elimination of the nitride oxidation mask and (if necessary) from the dense dislocation network 20, region in which no did not form a bird beak.
  • step (A) it is possible to carry out step (A) after step (B) provided that the ionic energy is large enough to perform the implantation operation through the nitride layer.
  • the choice of ions is mainly determined by the fact that in most cases they should not react electrically with silicon. For example, Si, Ge, Ar, Ne and O are possible bodies.
  • the energy of the implantation controls the depth of the damaged region.
  • the dose of ions must be close to the critical dose for a continuous amorphous layer to be effectively formed in the silicon, for example a dose of between 5 ⁇ 10 and 10 ⁇ 10 ions per cm 2 (for argon in silicon) is suitable.
  • step (F) may not be necessary in the manufacture of bipolar devices but may be necessary in the manufacture of MOS type field effect transistors.

Abstract

- Perfectionnement aux procédés de fabrication de dispositifs semi-conducteurs. -Ce procédé évite l'apparition du phénomènedit du "bec d'oiseau" et permet cependant, le dépôt direct du masque en Si3N4 sur le substrat de silicium. Il comporte les étapes suivantes; (A) élaboration d'un substrat semi-conducteur typiquement de silicium (10); (B) implantation d'ions neutres (argon) dans la couche superficielle (20) du substrat pour l'endommager, et la rendre quasiment amorphe, cette étape est suivie d'un recuit; (C) formation sur ladite couche d'un masque (14) en nitrure de silicium (Si3N4) selon une configuration désirée; (D) oxydation des portions exposées du substrat pour former des régions (16) de bioxyde de silicium encastrées. -Application à la fabrication de dispositifs semiconducteurs à isolement par des régions en matériau diélectrique encastrées à grande densité d'intégration.- Improvement in the manufacturing processes of semiconductor devices. -This process avoids the appearance of the phenomenon of the "bird's beak" and nevertheless allows the direct deposition of the mask in Si3N4 on the silicon substrate. It includes the following steps; (A) preparation of a typically silicon semiconductor substrate (10); (B) implantation of neutral ions (argon) in the surface layer (20) of the substrate to damage it, and make it almost amorphous, this step is followed by annealing; (C) forming on said layer a mask (14) of silicon nitride (Si3N4) according to a desired configuration; (D) oxidation of the exposed portions of the substrate to form embedded regions (16) of silicon dioxide. -Application to the manufacture of semiconductor devices insulated by regions of embedded dielectric material with high integration density.

Description

DescriptionDescription Domaine de l'inventionField of the invention

La présente invention concerne, la fabrication de dispositifs semi-conducteurs comportant des régions d'oxyde encastrées et plus particulièrement, un procédé d'application directe d'un masque de nitrure sur un substrat, typiquement de silicium, préalablement endommagé par une étape d'implantation ionique suivie par un recuit.The present invention relates to the manufacture of semiconductor devices comprising embedded oxide regions and more particularly to a method of direct application of a nitride mask on a substrate, typically of silicon, previously damaged by a step of ion implantation followed by annealing.

Description de l'art antérieur et énoncé du problèmeDescription of the prior art and statement of the problem

Il est bien connu dans la fabrication des dispositifs semi-conducteurs comportant des régions d'oxyde encastrées qui sont délimitées par un masque composé par exemple par du nitrure de silicium, que simultanément à la croissance de la région d'oxyde épais, il se développe aussi une région d'oxyde mince en saillie au-dessous dudit masque. Cette saillie qui se trouve dans la zone où sera réalisée la région de porte dans le cas de la fabrication d'un dispositif MOS FET, est appelée "bec d'oiseau" en raison de son profil en forme de bec et sa présence est attribuée à une diffusion latérale d'oxygène sous la couche de dioxyde de silicium mince qui est disposée entre le masque de nitrure de silicium et la surface du substrat typiquement, de silicium. On utilise cette couche de dioxyde de silicium mince parce que le dépôt du masque de nitrure de silicium directement sur le substrat de silicium entraînerait des défauts provoqués par des contraintes et des dislocations dans le substrat de silicium qui affecteraient de façon défavorable les performances du dispositif. Malheureusement, l'utilisation de cette couche de dioxyde de silicium pour empêcher l'apparition de ces défauts entraîne la formation de ces becs d'oiseaux indésirables comme on l'a vu ci-dessus.It is well known in the manufacture of semiconductor devices comprising embedded oxide regions which are delimited by a mask composed for example of silicon nitride, that simultaneously with the growth of the thick oxide region, it develops also a thin oxide region projecting below said mask. This projection which is in the area where the door region will be produced in the case of the manufacture of a MOS FET device, is called "bird beak" because of its profile in the shape of a beak and its presence is attributed to a lateral diffusion of oxygen under the layer of thin silicon dioxide which is disposed between the mask of silicon nitride and the surface of the substrate typically, of silicon. We uses this thin silicon dioxide layer because depositing the silicon nitride mask directly on the silicon substrate would cause defects caused by stresses and dislocations in the silicon substrate which would adversely affect the performance of the device. Unfortunately, the use of this layer of silicon dioxide to prevent the appearance of these defects leads to the formation of these unwanted bird beaks as seen above.

Ce problème étant posé, il y a eu de nombreuses tentatives pour améliorer les procédés de fabrication et minimiser la formation de ces becs d'oiseaux, souvent en continuant à utiliser cette couche intermédiaire de dioxyde de silicium.This problem being posed, there have been many attempts to improve the manufacturing processes and minimize the formation of these bird beaks, often by continuing to use this intermediate layer of silicon dioxide.

Par exemple, le brevet des E.U.A. No. 3 961 999 décrit un procédé permettant de réduire les problèmes posés par l'apparition des becs d'oiseaux. Dans ce brevet, la couche de dioxyde de silicium est classiquement située entre le substrat de silicium et la couche de nitrure de silicium. Ce brevet précise que des trous sont d'abord réalisés par décapage dans le dioxyde de silicium; ces trous correspondent aux ouvertures pratiquées préalablement dans le masque de nitrure mais présentent un diamètre d'ouverture plus important. Le silicium du substrat est éliminé dans les trous. Une couche de silicium est donc déposée globalement sur toute la structure, puis cette dernière est oxydée. Les régions d'isolement diélectrique encastrées sont relativement planes, mais les problèmes posés par la présence des becs d'oiseaux ne sont pas totalement résolus.For example, US Patent No. 3,961,999 describes a method for reducing the problems posed by the appearance of bird beaks. In this patent, the layer of silicon dioxide is conventionally located between the silicon substrate and the layer of silicon nitride. This patent specifies that holes are first made by pickling in the silicon dioxide; these holes correspond to the openings previously made in the nitride mask but have a larger opening diameter. The silicon in the substrate is eliminated in the holes. A layer of silicon is therefore deposited overall over the entire structure, then the latter is oxidized. The recessed dielectric isolation regions are relatively flat, but the problems posed by the presence of bird beaks are not fully resolved.

Par exemple, le brevet des E.U.A No. 3 900 350 décrit une solution qui permet de réduire les becs d'oiseaux en utilisant une couche de silicium polycristallin sous le masque d'oxydation à la place de l'oxyde de silicium habituel. En outre ce brevet met en évidence les défauts créés par les contraintes, qui apparaissent lorsque le masque d'oxydation de nitrure de silicium est disposé directement sur le substrat de silicium.For example, U.S. Patent No. 3,900,350 describes a solution to reduce bird beaks by using a layer of polycrystalline silicon under the oxidation mask in place of the usual silicon oxide. In addition, this patent highlights the defects created by the stresses, which appear when the silicon nitride oxidation mask is placed directly on the silicon substrate.

Ces deux brevets sont classiques. Ils préconisent l'utilisation d'une couche intermédiaire placée entre le masque de nitrure et le substrat de silicium, en essayant de réduire au minimum les problèmes posés par les becs d'oiseaux.These two patents are classic. They recommend the use of an intermediate layer placed between the nitride mask and the silicon substrate, trying to minimize the problems posed by bird beaks.

Exposé de la présente inventionDisclosure of the present invention

Le procédé de la présente invention est intéressant par le fait qu'il élimine ce besoin de disposer d'une couche intermédiaire, entre le masque de nitrure et le substrat, et qui avait pour conséquence le développement de ces becs d'oiseaux. En outre le procédé de la présente invention permet au masque de nitrure d'être déposé directement sur le substrat de silicium tout en éliminant les défauts par contraintes qui apparaissaient habituellement avec cette pratique.The method of the present invention is interesting in that it eliminates the need for an intermediate layer, between the nitride mask and the substrate, which had the consequence of developing these bird beaks. In addition, the process of the present invention allows the nitride mask to be deposited directly on the silicon substrate while eliminating the stress defects which usually appear with this practice.

Le procédé de la présente invention comporte essentiellement l'étape d'endommagement initial de la surface du substrat de silicium par une implantation ionique jusqu'à une profondeur contrôlée, suivie ensuite de préférence par une étape de recuit pour créer un réseau dense de dislocations qui empêchera la propagation des défauts induits par contraintes à partir de la couche de masquage lorsque l'on procède à l'étape de dépôt d'un masque contre l'oxydation typiquement en nitrure de silicium directement sur la surface dudit substrat.The method of the present invention essentially comprises the step of initial damage to the surface of the silicon substrate by ion implantation to a controlled depth, then preferably followed by an annealing step to create a dense network of dislocations which prevent propagation of stress induced defects from the layer masking when proceeding to the step of depositing a mask against oxidation typically in silicon nitride directly on the surface of said substrate.

Dans une réalisation particulière le présent procédé comporte les étapes suivantes:

  • (A) élaboration d'un substrat semi-conducteur,
  • (B) implantation d'ions neutres pour endommager ledit substrat jusqu'à une profondeur contrôlée en créant un réseau dense de dislocations, et recuit
  • (C) formation d'un masque d'oxydation selon une configuration désirée directement sur la surface dudit substrat selon une configuration désirée,
  • (D) oxydation des régions du substrat exposées à travers les ouvertures dudit masque et
  • (E) élimination dudit masque.
In a particular embodiment, the present method comprises the following steps:
  • (A) development of a semiconductor substrate,
  • (B) implantation of neutral ions to damage said substrate to a controlled depth by creating a dense network of dislocations, and annealing
  • (C) formation of an oxidation mask in a desired configuration directly on the surface of said substrate in a desired configuration,
  • (D) oxidation of the regions of the exposed substrate through the openings of said mask and
  • (E) removing said mask.

D'autres objets, caractéristiques et avantages de la présente invention ressortiront mieux de l'exposé qui suit, fait en référence aux dessins annexés à ce texte, qui représentent un mode de réalisation préféré de celle-ci.Other objects, characteristics and advantages of the present invention will emerge more clearly from the following description, made with reference to the drawings appended to this text, which represent a preferred embodiment thereof.

Brève description des dessinsBrief description of the drawings

Les figures 1A, 1B et 1C représentent différentes étapes de la fabrication d'une région d'oxyde encastrée dans un substrat semi-conducteur typiquement de silicium en utilisant un masque pour l'oxydation composite: nitrure-dioxyde de silicium, tel qu'il est réalisé habituellement dans l'art antérieur.FIGS. 1A, 1B and 1C represent different stages of the manufacture of an oxide region embedded in a typically silicon semiconductor substrate using a mask for the composite oxidation: nitride-silicon dioxide, as it is usually carried out in the prior art.

Les figures 2A, 2B, 2C et 2D, illustrent différentes étapes de la fabrication d'une région d'oxyde encastrée dans un substrat semi-conducteur typiquement de silicium en utilisant un masque pour l'oxydation en nitrure, placé directement sur le substrat, après que ce dernier ait subi les étapes d'implantation ionique et de recuit conformément aux principes de la présente invention.FIGS. 2A, 2B, 2C and 2D, illustrate different stages of the fabrication of an oxide region embedded in a semiconductor substrate typically of silicon using a mask for nitride oxidation, placed directly on the substrate, after the latter has undergone the steps of ion implantation and annealing in accordance with the principles of the present invention.

Description détaillée du mode préféré de réalisationDetailed description of the preferred embodiment

Les figures 1A, 1B et 1C sont des vues en coupe qui représentent le phénomène de formation d'un bec d'oiseau. Sur la figure 1A, on représente un substrat de silicium 10 et un masque d'oxydation 14 en nitrure de silicium déposé sur la région désirée. Le masque de nitrure de silicium 14 est séparé du substrat 10 par une couche 12 de dioxyde de silicium, puisque, comme on l'a vu placer le masque de nitrure 14 directement sur le substrat 10 entraînerait des déformations par contraintes dans ce substrat et conduirait ainsi à des dispositifs faiblement performants.Figures 1A, 1B and 1C are sectional views which represent the phenomenon of formation of a bird's beak. In FIG. 1A, a silicon substrate 10 and an oxidation mask 14 made of silicon nitride deposited on the desired region are shown. The silicon nitride mask 14 is separated from the substrate 10 by a layer 12 of silicon dioxide, since, as we have seen, placing the nitride mask 14 directly on the substrate 10 would cause stress deformations in this substrate and would lead thus to poorly performing devices.

Sur la figure 1B, l'oxyde encastré 16 est obtenu par croissance thermique dans la région désirée non masquée et une saillie 16' apparaît sous le masque 14. Après l'étape d'oxydation, le masque 14 est éliminé tel que représenté sur la figure 1C. A cause de cette saillie relativement large d'oxyde de silicium 16', le long de la configuration d'oxyde encastré, une portion qui ressemble à un bec d'oiseau demeure après l'élimination du masque au nitrure 14 et de la couche d'oxyde mince sous-jacente 12, par un procédé de décapage approprié.In FIG. 1B, the embedded oxide 16 is obtained by thermal growth in the desired unmasked region and a projection 16 ′ appears under the mask 14. After the oxidation step, the mask 14 is removed as shown in the Figure 1C. Because of this relatively wide projection of 16 'silicon oxide, along the recessed oxide configuration, a portion that resembles a bird's beak remains after removal of the nitride mask 14 and the layer d 'underlying thin oxide 12, by an appropriate pickling process.

Cette portion en forme de bec d'oiseau produit un effet de masquage non désiré lors des procédés de diffusion ultérieurs et peut même déterminer la frontière latérale de la zone diffusée, auquel cas la jonction p-n formée entre la zone diffusée et le substrat peut présenter des bords courbés. Dans des étapes de fabrication ultérieures, lors de la fabrication de la zone diffusée il est même possible que la jonction p-n puisse être exposée à la surface du substrat.This beak-shaped portion produces an unwanted masking effect during diffusion processes and can even determine the lateral border of the scattered area, in which case the pn junction formed between the scattered area and the substrate may have curved edges. In subsequent manufacturing steps, during the fabrication of the diffused area it is even possible that the pn junction may be exposed on the surface of the substrate.

Comme décrit dans le brevet des E.U.A No. 3 900 350 sus-mentionné, on pourra utiliser une couche de silicium polycristallin au lieu et place de la couche de dioxyde de silicium. Cette couche de silicium polycristallin placée sur le substrat de silicium monocristallin réduit les contraintes dues au masque de nitrure et en même temps réduit à un minimum la saillie en forme de bec d'oiseau. Cependant cette technique met ainsi en oeuvre une couche intermédiaire relativement épaisse qui doit être enlevée soit directement, soit indirectement après conversion en oxyde, par une étape de décapage.As described in the aforementioned U.S. Patent No. 3,900,350, a polycrystalline silicon layer may be used in place of the silicon dioxide layer. This polycrystalline silicon layer placed on the monocrystalline silicon substrate reduces the stresses due to the nitride mask and at the same time reduces the projection in the shape of a bird's beak. However, this technique thus uses a relatively thick intermediate layer which must be removed either directly or indirectly after conversion to oxide, by a pickling step.

La figure 2A représente, en coupe, un substrat de silicium 10 qui a été soumis à un faisceau d'ions jusqu'à une profondeur contrôlée d. L'implantation ionique produit une couche très endommagée 20 pratiquement en silicium amorphe à la surface du substrat 10. Le substrat 10 est alors recuit et la couche fortement endommagée 20 génère un réseau de dislocation très dense, dont la microstructure dépend de l'énergie, de la dose et de la nature des ions utilisés pendant l'opération d'implantation.FIG. 2A represents, in section, a silicon substrate 10 which has been subjected to an ion beam to a controlled depth d. The ion implantation produces a very damaged layer 20 practically of amorphous silicon on the surface of the substrate 10. The substrate 10 is then annealed and the heavily damaged layer 20 generates a very dense dislocation network, the microstructure of which depends on energy, the dose and the nature of the ions used during the implantation operation.

Le réseau de dislocation dense obtenu après les étapes d'implantation et de recuit, protège le silicium monocristallin sous-jacent des défauts induits par. contraintes et permet au masque d'oxydation au nitrure 14 -d'être disposé directement sur le substrat 10 tel qu'illustré sur la figure 2B.The dense dislocation network obtained after the implantation and annealing steps, protects the mono silicon underlying lens of the defects induced by. constraints and allows the nitride oxidation mask 14 to be placed directly on the substrate 10 as illustrated in FIG. 2B.

La surface du substrat 10 après les étapes d'implantation et de recuit est aussi protégée contre l'oxydation de sorte qu'on n'obtient pas de saillie en forme de bec d'oiseau. Ainsi, la figure 2C illustre la structure après l'étape d'oxydation, et la figure 2D illustre la structure après l'élimination du masque d'oxydation au nitrure et (si nécessaire) du réseau de dislocations dense 20, région dans laquelle ne s'est pas formé de bec d'oiseau.The surface of the substrate 10 after the implantation and annealing steps is also protected against oxidation so that no projection in the form of a bird's beak is obtained. Thus, FIG. 2C illustrates the structure after the oxidation step, and FIG. 2D illustrates the structure after the elimination of the nitride oxidation mask and (if necessary) from the dense dislocation network 20, region in which no did not form a bird beak.

Un exemple de fabrication d'une réalisation particulière peut être décrit de la façon suivante:

  • Etape (A) : élaboration d'un substrat de silicium (10);
  • Etape (B) : implantation d'ions Ar dans le substrat . de silicium 10 avec une énergie d'implantation de 20KeV, une dose totale d'en- viron 1015at.cm-2, pour constituer la couche 20 qui peut alors être recuite par les techniques classiques;
  • Etape (C) : dépôt à faible température de Si3N4 jusqu'à atteindre une épaisseur de 0 l'ordre de 300 à 1000 A pour réaliser la couche 14; et délimitation dudit masque d'oxydation en Si3N4 par des procédés appropriés (par exemple photolithographiques) pour obtenir la configuration désirée;
  • Etape (D) : oxydation jusqu'à l'obtention d'une épaisseur désirée: 6500 A par exemple, par exposition à des atmosphères alternativement séche-humide-séche;
  • Etape (E) : élimination du masque d'oxydation en Si3N4 par un procédé classique tel que le décapage par un mélange d'acide HF tamponné et d'acide phosphorique concentré;
  • Etape (F) : élimination de la couche de silicium endommagée, si cela est nécessaire, soit par décapage de la couche de silicium 0 (environ 500 A) soit par oxydation de la région endommagée: (croissance de SiO2 jusqu'à environ 1000 A, suivie de l'élimination par décapage, de l'oxyde ainsi formé.
A manufacturing example of a particular embodiment can be described as follows:
  • Step (A): development of a silicon substrate (10);
  • Step (B): implantation of Ar ions in the substrate. silicon 10 with an energy of 20KeV of implantation, a total dose of en- vi ron 10 at.cm 15 -2, to form the layer 20 which may then be annealed using conventional techniques;
  • S tep (C): deposit low temperature of Si 3 N 4 to a thickness 0 of about 300 to 1000 A to produce the layer 14; and delimiting said Si 3 N 4 oxidation mask by suitable methods (for example photolithographic) to obtain the desired configuration;
  • Step (D): oxidation until a desired thickness is obtained: 6500 A for example, by exposure to alternately dry-wet-dry atmospheres;
  • Step (E): elimination of the Si 3 N 4 oxidation mask by a conventional method such as pickling with a mixture of buffered HF acid and concentrated phosphoric acid;
  • Step (F): elimination of the damaged silicon layer, if necessary, either by etching of the silicon layer 0 (around 500 A) or by oxidation of the damaged region: (growth of SiO 2 up to around 1000 A, followed by removal by pickling, of the oxide thus formed.

Il est possible de réaliser l'étape (A) après l'étape (B) pourvu que l'énergie ionique soit suffisamment importante pour réaliser l'opération d'implantation à travers la couche de nitrure. Le choix des ions est déterminé principalement par le fait qu'ils ne doivent pas, dans la plupart des cas, réagir électriquement avec le silicium. Par exemple, Si, Ge, Ar, Ne et O sont des corps possibles.It is possible to carry out step (A) after step (B) provided that the ionic energy is large enough to perform the implantation operation through the nitride layer. The choice of ions is mainly determined by the fact that in most cases they should not react electrically with silicon. For example, Si, Ge, Ar, Ne and O are possible bodies.

L'implantation d'ions de silicium quand elle est utilisée pour améliorer la qualité du silicium est connue. La publication de S.M. Hu parue dans "IBM Technical Disclo- sure Bulletin", Vol. 19, No.2, juillet 1976, intitulée "Hardening Silicon Wafers by Ion Implantation" décrit cette technique pour réduire les dislocations dans des tranches de silicium soumises à des contraintes thermiques.The implantation of silicon ions when it is used to improve the quality of silicon is known. The publication of SM Hu appeared in "IBM Technical Disclosure Bulletin", Vol. 19, No.2, July 1976, entitled "Hardening Silicon Wafers by Ion Implantation" describes this technique to reduce dislocations in silicon wafers subjected to thermal stresses.

L'énergie de l'implantation commande la profondeur de la région endommagée. La dose d'ions devra être proche de la dose critique pour qu'il se forme effectivement une couche amorphe continue dans le silicium, par exemple une dose comprise entre 5 x 10 et 10 x 10 ions par cm2 (pour de l'argon dans du silicium) convient. En outre, on notera que l'étape (F) peut ne pas être nécessaire dans la fabrication des dispositifs bipolaires mais l'être dans la fabrication des transistors à effet de champ de type MOS.The energy of the implantation controls the depth of the damaged region. The dose of ions must be close to the critical dose for a continuous amorphous layer to be effectively formed in the silicon, for example a dose of between 5 × 10 and 10 × 10 ions per cm 2 (for argon in silicon) is suitable. In addition, it will be noted that step (F) may not be necessary in the manufacture of bipolar devices but may be necessary in the manufacture of MOS type field effect transistors.

Application industrielleIndustrial application

Ce qui a été décrit ci-dessus est donc un procédé amélioré de fabrication de dispositifs semi-conducteurs dans lequel le phénomène appelé "bec d'oiseau" est éliminé, en soumettant un substrat semi-conducteur à une implantation ionique de façon à générer un réseau de dislocation, la couche superficielle ainsi endommagée pouvant recevoir directement un masque de nitrure sans qu'une couche de dioxyde de silicium intermédiaire soit nécessaire. Ce procédé est donc d'un grand intérêt dans le domaine de la fabrication de dispositifs intégrés à semi-conducteurs à grande densité en particulier ceux isolés par des régions de matériau diélectrique encastrées.What has been described above is therefore an improved method of manufacturing semiconductor devices in which the phenomenon called "bird's beak" is eliminated, by subjecting a semiconductor substrate to ion implantation so as to generate a dislocation network, the surface layer thus damaged being able to directly receive a nitride mask without an intermediate layer of silicon dioxide being necessary. This process is therefore of great interest in the field of manufacturing high density semiconductor integrated devices, in particular those isolated by regions of embedded dielectric material.

Bien que l'on ait décrit dans ce qui précède et représenté sur les dessins les caractéristiques essentielles de l'invention appliquées à un mode de réalisation préféré de celle-ci, il est évident que l'homme de l'art peut y apporter toutes modifications de forme ou de détail qu'il juge utiles, sans pour autant sortir du cadre de ladite invention.Although the essential characteristics of the invention applied to a preferred embodiment of the invention have been described in the foregoing and represented in the drawings, it is obvious that a person skilled in the art can provide all of them. form changes or details that he deems useful, without going beyond the scope of said invention.

Claims (9)

1. Procédé de fabrication de dispositifs semi-conducteurs comportant des régions d'oxyde encastrées réalisées à partir d'un masque formé directement sur un substrat, caractérisé en ce qu'il comporte les étapes suivantes: (A) élaboration d'un substrat semi-conducteur, (B) implantation d'ions neutres pour endommager ledit substrat jusqu'à une profondeur contrôlée en créant un réseau dense de dislocations, (C) formation d'un masque d'oxydation directement sur la surface dudit substrat selon une configuration désirée, (D) oxydation des régions du substrat exposées à travers les ouvertures dudit masque et (E) élimination dudit masque. 1. Method for manufacturing semiconductor devices comprising embedded oxide regions produced from a mask formed directly on a substrate, characterized in that it comprises the following steps: (A) development of a semiconductor substrate, (B) implantation of neutral ions to damage said substrate to a controlled depth by creating a dense network of dislocations, (C) formation of an oxidation mask directly on the surface of said substrate in a desired configuration, (D) oxidation of the regions of the exposed substrate through the openings of said mask and (E) removing said mask. 2. Procédé selon la revendication 1 caractérisé en ce qu'il comporte en outre l'étape: (F) d'élimination de la couche superficielle endommagée dudit substrat. 2. Method according to claim 1 characterized in that it further comprises the step: (F) removing the damaged surface layer from said substrate. 3. Procédé selon la revendication 1 ou 2 caractérisé en ce que les étapes (B) et (C) sont inversées.3. Method according to claim 1 or 2 characterized in that steps (B) and (C) are reversed. 4. Procédé selon la revendication 1, 2 ou 3 caractérisé en ce que ledit masque est constitué par du Si 3 N4. 4. Method according to claim 1, 2 or 3 characterized in that said mask consists of S i 3 N 4 . 5. Procédé selon la revendication 1, 2, 3 ou 4 caractérisé en ce que l'étape (B) est suivie par une étape de recuit.5. Method according to claim 1, 2, 3 or 4 characterized in that step (B) is followed by an annealing step. 6. Procédé selon l'une quelconque des revendications ci-dessus caractérisé en ce que le substrat semi-conducteur est un substrat silicium monocristallin.6. Method according to any one of the above claims, characterized in that the semiconductor substrate is a monocrystalline silicon substrate. 7. Procédé selon la revendication 6 caractérisé en ce que lesdits ions neutres sont choisis dans le groupe comprenant Ar, Ge, Ne, O et Si.7. Method according to claim 6 characterized in that said neutral ions are chosen from the group comprising Ar, Ge, Ne, O and Si. 8. Procédé selon la revendication 7 caractérisé en ce que lesdits ions neutres sont des ions Ar, la dose implantée étant voisine de la dose critique pour transformer la couche superficielle du substrat silicium en du silicium amorphe.8. Method according to claim 7 characterized in that said neutral ions are Ar ions, the implanted dose being close to the critical dose for transforming the surface layer of the silicon substrate into amorphous silicon. 9. Procédé selon la revendication 8 caractérisé en ce que ladite dose est comprise entre 5 x 1014 et 10 x 1014 ions.cm-2.9. Method according to claim 8 characterized in that said dose is between 5 x 10 14 and 10 x 10 14 ions.cm -2 .
EP78430001A 1977-06-03 1978-06-01 Method of manufacturing semiconductor devices comprising recessed silicon oxide regions Expired EP0000316B1 (en)

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