DK157634C - TWO CHANNEL MICRODATA COMPUTER UNIT, NAME FOR RAILWAY SAFETY PLANT - Google Patents
TWO CHANNEL MICRODATA COMPUTER UNIT, NAME FOR RAILWAY SAFETY PLANTInfo
- Publication number
- DK157634C DK157634C DK074283A DK74283A DK157634C DK 157634 C DK157634 C DK 157634C DK 074283 A DK074283 A DK 074283A DK 74283 A DK74283 A DK 74283A DK 157634 C DK157634 C DK 157634C
- Authority
- DK
- Denmark
- Prior art keywords
- data buses
- channel
- external data
- address
- converters
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
Abstract
1. Two-channel fail-safe microcomputer switching network, in particular for railway security systems, having microcomputers (MC1, MC2) processing the same information in two channels, the data buses (DB1, DB2) of which microcomputers are connected via two coupling circuits (EV1, EV2) to each of two external data buses (DB10, DB20), to which input signal converters (E1, E2) and output signal converters (A1, A2) are connected which are selected with the aid of adresses given via an adress bus (ADB1, ADB2) of the associated microcomputer and can be activated by means of read or write signals (lOR1, lOR2, lOW1, lOW2) given via control lines (ST11, ST12, ST21, ST22) of the respective microcomputer, the two external data buses (DB10, DB20) being activated temporally staggered during the input phases in such a manner that the input signal converters (E1, E2) present in pairs on the two external data buses only become effective after one another with respect to the same information, characterized in that there is provided in each of the two channels between the control lines (ST11, ST12, or ST21, ST22) and the converters (E1, A1 or E2, A2) a control circuit (SG1, SG2), to which and to the respective coupling circuit (EV1 or EV2) in each case there are connected a first and a second address line (AL71, AL81 or AL72, AL82) of the associated address bus (ADB1 or ADB2), in conjunction with a channel-specific identifier ("L", "H), the control line (ST11 or ST21) carrying the read signal (lOR1 or lOR2) being additionally connected to the coupling circuit (EV1 or EV2) of the respective channel in such a manner that, per channel, the external data buses are switched off by the internal data buses (DB10/DB1 ; DB20/DB2) and the control circuit is switched off by the converters (SG1/E1, A1 ; SG2/A2) in the case of one value ("L") of the address bit (2**7) output via the first address line (AL71 or AL72), and in the case of the other value ("H") of this address bit (2**7), upon the presence of read signals (lOR1 or lOR2) by means or equivalence combination of the respective value ("L" or "H"), of the address bit (**8) of the second address line (AL81 or AL82) with the channel-specific identifier ("L" or "H"), an alternating data input takes place from one or the other external data bus (DB10 or DB20) to in each case both internal data buses (DB1, DB2).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3211265A DE3211265C2 (en) | 1982-03-26 | 1982-03-26 | Two-channel fail-safe microcomputer switchgear, especially for railway safety systems |
DE3211265 | 1982-03-26 |
Publications (4)
Publication Number | Publication Date |
---|---|
DK74283D0 DK74283D0 (en) | 1983-02-21 |
DK74283A DK74283A (en) | 1983-09-27 |
DK157634B DK157634B (en) | 1990-01-29 |
DK157634C true DK157634C (en) | 1990-07-02 |
Family
ID=6159437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DK074283A DK157634C (en) | 1982-03-26 | 1983-02-21 | TWO CHANNEL MICRODATA COMPUTER UNIT, NAME FOR RAILWAY SAFETY PLANT |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0090162B1 (en) |
AT (1) | ATE42846T1 (en) |
DE (1) | DE3211265C2 (en) |
DK (1) | DK157634C (en) |
ZA (1) | ZA832142B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3412049A1 (en) * | 1984-03-30 | 1985-10-17 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | SIGNAL-SAFE DATA PROCESSING DEVICE |
DE3938501A1 (en) * | 1989-11-20 | 1991-05-23 | Siemens Ag | METHOD FOR OPERATING A MULTI-CHANNEL FAILSAFE COMPUTER SYSTEM AND DEVICE FOR IMPLEMENTING THE METHOD |
CH683953A5 (en) * | 1992-04-30 | 1994-06-15 | Siemens Integra Verkehrstechni | Procedure to improve the signal-related safety of the user interface of a data processing system. |
DE102009045000A1 (en) * | 2009-09-25 | 2011-03-31 | Robert Bosch Gmbh | Method and data output monitoring unit for ensuring data output from error-free data of a data processing unit to a data bus |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2612100A1 (en) * | 1976-03-22 | 1977-10-06 | Siemens Ag | DIGITAL DATA PROCESSING ARRANGEMENT, IN PARTICULAR FOR RAILWAY SAFETY TECHNOLOGY |
-
1982
- 1982-03-26 DE DE3211265A patent/DE3211265C2/en not_active Expired
-
1983
- 1983-02-14 EP EP83101408A patent/EP0090162B1/en not_active Expired
- 1983-02-14 AT AT83101408T patent/ATE42846T1/en not_active IP Right Cessation
- 1983-02-21 DK DK074283A patent/DK157634C/en not_active IP Right Cessation
- 1983-03-25 ZA ZA832142A patent/ZA832142B/en unknown
Also Published As
Publication number | Publication date |
---|---|
ZA832142B (en) | 1983-12-28 |
DK74283A (en) | 1983-09-27 |
EP0090162A3 (en) | 1987-02-04 |
DK157634B (en) | 1990-01-29 |
EP0090162B1 (en) | 1989-05-03 |
DE3211265C2 (en) | 1984-06-20 |
DK74283D0 (en) | 1983-02-21 |
EP0090162A2 (en) | 1983-10-05 |
DE3211265A1 (en) | 1983-10-06 |
ATE42846T1 (en) | 1989-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3485467D1 (en) | SELF-CHECKING COMPUTER ARRANGEMENT. | |
DK220883A (en) | MULTIPROCESSOR COMPUTER SYSTEM | |
ATE230179T1 (en) | CONTROL AND COMMUNICATION DEVICE | |
ATE9619T1 (en) | DEVICE FOR CONTROLLING THE ACCESS OF PROCESSORS TO A DATA LINE. | |
DK157634C (en) | TWO CHANNEL MICRODATA COMPUTER UNIT, NAME FOR RAILWAY SAFETY PLANT | |
JPH033253B2 (en) | ||
KR950035209A (en) | Horizontally distributed network system and multiprocessor system | |
SU637816A1 (en) | Three-channel redundancy arrangement | |
JPS6095678A (en) | Multi-processor system | |
SU868761A2 (en) | Controllable-structure redundancy device | |
SU605217A1 (en) | Arrangement for switching system reserved units | |
SU457990A1 (en) | Redundant system | |
GB1412177A (en) | Programme controlled data processing systems | |
JPH063587B2 (en) | Synchronous operation method of dual microprocessor | |
JP2612715B2 (en) | Address bus controller | |
JPS62182953A (en) | Memory access control system | |
SU574719A1 (en) | Redundancy device | |
JPS63182933A (en) | Identification number assignment method | |
SU955539A1 (en) | Majority redundancy device | |
RU1805477C (en) | Multiprocessor computing system | |
JPH01159729A (en) | Symbol string collation memory and its cascade connection system | |
SU868745A1 (en) | Interface | |
JPH0562786B2 (en) | ||
SU478310A1 (en) | Redundant device | |
JPH04109350A (en) | Data write control device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PBP | Patent lapsed |