SU868761A2 - Controllable-structure redundancy device - Google Patents

Description

one

The invention relates to automation and computing, can be used in the development of redundant devices.

According to the main author. St. No. 565298, known is a redundant device with a controlled structure, comprising three redundant blocks and three controlled major blocks, the control inputs of which are connected to the control bus of the device, a mode setting block and three AND elements, the first inputs of which are connected to the outputs of redundant blocks, the second outputs of the And elements are connected respectively to the first, second, and third outputs of the mode setting unit, the fourth output of which is connected to the common control bus of the device, the outputs of the And elements are connected nnym inputs actuated majority Bloch, Kow 1.

A disadvantage of this device is that in the test mode, the outputs of the redundant blocks must be logical, and this, given the known structure of the device, reduces the reliability of the control, since in the event of a failure of at least one of the redundant blocks.

a reliable verification of controlled majority blocks is impossible, since the output of a faulty block is my logical O.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by introducing three elements OR into the device, the first inputs of which are connected to the outputs of the reserved blocks, the second inputs to the common control bus of the device, and the outputs to the first inputs of the elements I.

The drawing shows a block diagram of the proposed device.

The device contains a common control bus 1, controllable majority blocks 2, i / elements And 3, 3 / and 3, redundant blocks 4 |, 4 and

20 4 (j ,, control buses 5, 5 and 5, output buses 6, 62. and 6 devices, mode setting block 7, information inputs 8, 9, 9, 10g and 10-j, controlled by majority

25 blocks, elements OR 11, 12, 13, element AND 14, counter 15, decoder 16 and receiving node 17, elements OR, IQ to 18 ,. Elements 11-14 constitute a controllable majority unit, and elements 15-17 constitute a task block. In the test mode, at the initial time, the counter 15 is recorded, and from the decoder 16 to the common control bus 1 and to the second inputs of the elements OR 18, iSg., 18, a signal is supplied, switching all the units 2, 2, 2 to the parallel independent mode the work and simulation of the outputs of the elements OR 18, 18, 18 are logical, a signal is sent to the bus 5 allowing the logical passage from the element OR 18 ,, through the AND 3 element to the inputs 8, 9 / and 9h, blocks 2, 2,

respectively; Si and 5 buses are banned and signals are missing at inputs 83, 8 g of blocks 2 and 2, and there are no signals.

/

(presence of logical O). Thus, regardless of the state of the outputs of the reserved blocks 4, 4 /) and 4

 , 1J2. and 4-J at output 6 of block 2 should be logical, and at 6 2. and 6

block 2i2 and 2 must be logical O, which is fixed by the receiving node 17 of block 7

When serving next

In counter 15, the enabling signal is fed to the tires 5.2. At the same time, there is a signal on the common control bus 1 and respectively on the second inputs of the elements OR 18; 18 and 18. At the same time

a logical unit must be present on bus 6 and absent on buses 6 and 6.,

Further operation of the device in the test mode is similar.

The proposed device makes it possible to carry out a complete check of the operability of blocks 2, 2.2 and 2 regardless of the state of the outputs of the blocks being reinstated and, based on the checked blocks 2, 2 and 2, to check the redundant equipment in the process of regulation and operation, which increases reliability of operation.

Claims (1)

1. USSR author's certificate No. 565298, - cl. G 06 F 11/00, 1975 (prototype).