SU822391A1 - Device for control of switching-over the reserve - Google Patents

Description

one

The invention relates to automation and computer technology and can be used in the construction of high reliability systems.

A redundant system control device is known that contains a counter connected to a decoder whose outputs are OR elements connected to power switches of redundant units, AND, OR elements and ij matching schemes.

The disadvantage of the known device is the loss of its working capacity with the simultaneous failure of two working blocks. Thus, a redundant system consisting of four redundant blocks becomes inoperable in the event of a failure of two blocks, which reduces the reliability of the redundant system. In addition, this device is sensitive to single sbo.

A device for controlling the switching of a reserve is known, comprising a counter connected via a decoder to the power switches of the reserved blocks, mismatch elements, AND, OR, generator, pulses, delay element, memory element. This device has a dvg

workers and two backup units. Such a device makes it possible to search for a serviceable pair of blocks when one of the working blocks fails, as well as when two blocks fail when the device fails to fix one of the blocks. devices ..

However, this device loses

0 its performance in case of simultaneous failure of the two blocks 1 and 2 initially included in the operation. In addition, this device is sensitive to single failure of M 2.

five

The closest technical solution to the present invention is a control and switching reserve device comprising a first switching counter connected to a decoder, the outputs of which are connected to the control switches of the 1EP power switch, the outputs of which are connected to the first inputs of the AND elements and redundant units ,

5 outputs of which are connected to the inputs of the first element .OR and the first inputs of the mismatch elements, the second inputs of which are connected to the output of the first element OR, and the outputs - with

0 second inputs of elements And outputs

which are connected via the second OR element to the counting input of the fault counter, the installation input of which is connected to the reset counter output, the output of the last bit of the Sb.oi counter is connected to the counting input of the first switching counter, and the outputs of the other bits are connected to the inputs of the third OR element.

The principle of operation of this redundant device, where two units work and two are in reserve, is based on finding a working pair of blocks if one of the working blocks fails.

However, if a pair of blocks is initially turned on at the same time, the mismatch elements do not work, so the fault counter remains in the initial state, which means that the supply voltage does not switch to the next combination of redundant blocks. This can also occur in case of successive failure of two initially operated blocks in the time interval defined by the fault counter. Thus o6pa3otvj, a redundant system of four blocks when a failure of two blocks becomes inoperable, this reduces the reliability of the redundant system.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the device contains an edge selector, a second switching counter, a three-input element AND, and a two-input element AND, connected by an output to the counting input of a reset counter, one input - to the output of the third element OR, and another input - to the clock input of the device and the counting input the second switching counter, the setup input of which is connected via .; the edge selector to the output of the first OR element, and the output to the first input of the three-input element AND, the second and third inputs of which are connected to the outputs of the first and second power switches, and the output of the three-input element AND connected to the installation, input of the first switching counter.

The drawing shows a functional diagram of the device.

The scheme contains blocks 1-4 of the redundant system, the first element OR 5 elements bt-E mismatch, elements AND 10-13, the second element OR 14, the counter 15 failures, the third element OR 16, the counter 17 reset, the first counter 18 switching, the decoder 19, the selector 20 of the fronts, the second counter 21 switching, elements And 22 and 23, the switches 24-27 power input 28 and the output 29 of the redundant system, the clock input 30 of the device

Switched power sources 31-34.

The device works as follows.

At the initial time, the counter 15 failures, the reset counter 17, and the second switching counter 21 are in the zero state (the initial state setting in the drawing is conventionally not shown), and the switching number counter 18 is in the state in which the decoder 19 turns on through switches 24 and 25 of power supply, blocks 1 and 2, blocks 3 and 4 are disconnected. During proper operation, blocks 1 and 2 produce signals that coincide with the signals at the output of the element OR 5, therefore zero signals are output at the outputs of the mismatch elements, and the fault counter 15 stores the zero state. The zero state of the last digit of the counter 15 does not change the initial state of the counter 18, and the zero state of its previous bits closes the receipt of clock signals through the two-input element And 23 to the counting input of the reset counter 17, as a result of which the latter retains the zero state. The clock signals, which appear only at the time of output of the output signals of the device, arrive at the counting input of the second counter 21 of switches, changing its state. However, when the element OR 5 changes its zero state to a single or vice versa, the selector 20 of the fronts generates a signal that sets the counter 21 to the zero state, preventing it from overflowing when the blocks 1 and 2 work properly. The first switching counter 18 does not receive a switching signal, therefore, it retains its original state, leaving the initial combination of reserved blocks enabled.

Let, due to a failure or malfunction in one of the included blocks, for example in block 1, its output signals do not coincide with the output signals of the element OR 5, then element 6 generates a mismatch signal that passes through the open during device presence at the clock input 30 of the device the element AND 10 and through the element OR 14 to the counting input of the counter 15 fail, changing its state. The signal from the output of the counter 15 through the element OR 16 allows the passage of clock signals through the element And 23 to the counting input of the counter. 17 reset. The number of bits of the counters 15 and 17 is chosen so as to provide the criterion of switching the reserve, namely the sensitivity of the switching device to a certain number of failures over a certain time interval. In this case, counter 15 has the number of bits that allow counting the maximum permissible number of signal failures for a given system for a certain time interval, which is counted by counter 17 If the number of failures for a certain interval is less than the allowable one, counter 15 overflows to the zero state, and the operation cycle begins again. When the number of failures over a certain interval is more than permissible for this system, then counter 15 has time to overflow during the filling time of counter 17 and outputs a signal to the counter input of counter 18 ,. which through the decoder 19 and the corresponding switches includes the power supply voltage — to the next combination of redundant blocks.

If different types of failures occur simultaneously in two blocks 1 and 2 (block 1 is false O, block 2 is false 1), the device searches for an operable pair of blocks 3 and 4 in the following way, in this case, counters 15 and 21 produce a count of clock pulses arrive at their counting inputs from the bus 30. Counter 15 is activated due to the fact that the mismatch element 6 generates a mismatch signal that acts on the second input of the AND 10 element, allowing passage through it and the OR element 14 on the counting input of the specified clock pulse counter ov In this case, the counter 15 outputs a signal to the counting input of the counter 18, as a result of which using the decoder 19 and the corresponding switches 2427, the power supply voltage for the next combination of backup units is turned on. After this switch, counters 17 and 21 are reset to the initial pulse. initial state. The search for serviceable blocks continues until the supply voltage is turned on to an operable pair of blocks 3 and 4. Counter 21 Switches to the clock pulse counting mode due to the fact that the frontier 20 is separated (due to the presence of a potential level coming at its input from the output block 2 through the OR element 5) does not generate signals for setting the specified counter to the zero state. The counter 21 is tuned to the number of clock pulses that fits in the interval between two successive single information word signals spaced apart from each other in time. The overflow signal of the counter 21 is supplied through the AND element 22 to the installation input of the switching counter 18 and sets it to this state, when

which the decoder 19 includes through the switches 33 and 34 backup blocks 3 and 4. Since the information on the outputs of the blocks, as a rule, is presented in the form of single and zero signals, and the time between successive single signals, may be different depending on the structure of information words used in different systems, the number of bits of counters 15 and 21 may be different.

In systems in which one of the information words may consist mainly of zero signals and, therefore, the maximum interval

the time between successive single signals can be a relatively large value, in this case the number of bits of the counter 21 is chosen large compared to the number of bits of the counter 15. Thus, the overflow signal of the counters 15 or 21 through the counter 18 and the decoder 19 performs switching power on nai5y blocks 3-4.

Since informational words consist of alternating zero and single signals, for some time

At the outputs of the working blocks, zero signals will be present at the output of the clock pulses (there will be no signaling changes). In this case, a false switch to another pair of blocks will not occur, since the second switching counter 21, after some filling with its clock pulses, is reset to its original state. This is due to the fact that there is a change in the level of the output signals of the working blocks, since the information words consist of alternating zero and single signes. Therefore, the edge driver 20, when the level of the information signals changes, will trigger and set the counter 21 to the zero state.

Claims (3)

If at some point in time when the blocks 1 and 2 are working, the device was damaged, as a result of which the blocks were lowered out of order, and their outputs would be in the same state, then the mismatch elements 6 and 7 do not generate signals and counters 15 and 17 preserve the zero state, therefore, cannot switch the blocks. At the output of the element OR 5, in the absence of changes at its inputs, the state does not change, therefore, the edge selector 20 does not reset the counter 21 to the zero state, and s signals to the count input of counter 21 to cause its overflow. As a result, the counter 21 selects a signal that passes through the open three-input element And 22 and sets the counter 18 to such a state. wherein the decoder 19 switches on through switches 33 and 34 backup blocks 3 and 4. Counter 21 is tuned to a certain number of clock signals, which fill it in the interval between two unit-output signals of the device. Thus, at simultaneous failure of blocks 1 and 2 the redundant device remains operational. The technical and economic effect of the use of this device consists in a significant increase in the operational reliability of the device as with one volume and one volume. however, the number of units of the redundant system, it provides a much higher reliability of the entire system as a whole, i.e. increases time-trouble-free operation of the system. Claims An inventive switching control device comprising a first switching counter connected to a decoder, the outputs of which are connected to the control inputs of power switches, the outputs of which are connected to the first inputs of the AND elements and backed up by blocks and outputs whose connections are connected to the inputs of the first OR element and the first the inputs of the mismatch elements, the second inputs of which are connected to the output of the first element OR, and the outputs to the second inputs of the AND elements, the outputs of which through the second element OR Connected to the counting input of the fault counter, the setup input of which is connected to the output of the reset counter, the output of the last bit of the failure counter to the counting input of the first switching counter, and the other bits of the bit connected to the inputs of the third OR element, characterized in that device reliability, it contains an edge remover, a second switching counter, a three-input element And, and a two-input element And connected by an output to the counting input of a reset counter, one input - to the output of the third IL element and the other input to the clock input of the device and the counting input of the second switching counter, the setup input of which is connected via the edge selector to the output of the first OR element, and the output to the first input of the three-input element AND, the second and third inputs of which are connected to the outputs of the first and the second power switch, and the output of the three-input element And is connected to the installation input of the first switching counter. Sources of information taken into account in the examination 1. USSR author's certificate number 357694, cl. And 05 K 10/00, 1970. 2. USSR author's certificate number 546889, cl. G About F 11/00, 1974. 3. USSR author's certificate number 552737, cl. H 05 K 10/00, 1975 (prototype).