DE69935357D1 - Vorrichtung zur Faltungsverschachtelung - Google Patents

Vorrichtung zur Faltungsverschachtelung

Info

Publication number
DE69935357D1
DE69935357D1 DE69935357T DE69935357T DE69935357D1 DE 69935357 D1 DE69935357 D1 DE 69935357D1 DE 69935357 T DE69935357 T DE 69935357T DE 69935357 T DE69935357 T DE 69935357T DE 69935357 D1 DE69935357 D1 DE 69935357D1
Authority
DE
Germany
Prior art keywords
nesting
convolution
convolution nesting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69935357T
Other languages
English (en)
Other versions
DE69935357T2 (de
Inventor
Senichi Furutani
Yasuhiro Nakakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69935357D1 publication Critical patent/DE69935357D1/de
Publication of DE69935357T2 publication Critical patent/DE69935357T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations
DE69935357T 1998-04-27 1999-04-27 Vorrichtung zur Faltungsverschachtelung Expired - Lifetime DE69935357T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11734298 1998-04-27
JP11734298 1998-04-27

Publications (2)

Publication Number Publication Date
DE69935357D1 true DE69935357D1 (de) 2007-04-12
DE69935357T2 DE69935357T2 (de) 2007-11-29

Family

ID=14709342

Family Applications (4)

Application Number Title Priority Date Filing Date
DE69922732T Expired - Lifetime DE69922732T2 (de) 1998-04-27 1999-04-27 Verfahren und Vorrichtung zur Faltungsverschachtelung sowie Verfahren und Vorrichtung zur Faltungsentschachtelung
DE69935356T Expired - Lifetime DE69935356T2 (de) 1998-04-27 1999-04-27 Verfahren zur Faltungsentschachtelung
DE69935357T Expired - Lifetime DE69935357T2 (de) 1998-04-27 1999-04-27 Vorrichtung zur Faltungsverschachtelung
DE69935358T Expired - Lifetime DE69935358T2 (de) 1998-04-27 1999-04-27 Verfahren zur Faltungsverschachtelung

Family Applications Before (2)

Application Number Title Priority Date Filing Date
DE69922732T Expired - Lifetime DE69922732T2 (de) 1998-04-27 1999-04-27 Verfahren und Vorrichtung zur Faltungsverschachtelung sowie Verfahren und Vorrichtung zur Faltungsentschachtelung
DE69935356T Expired - Lifetime DE69935356T2 (de) 1998-04-27 1999-04-27 Verfahren zur Faltungsentschachtelung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69935358T Expired - Lifetime DE69935358T2 (de) 1998-04-27 1999-04-27 Verfahren zur Faltungsverschachtelung

Country Status (6)

Country Link
US (1) US6411654B1 (de)
EP (4) EP0954109B1 (de)
KR (1) KR100330608B1 (de)
CN (2) CN100358243C (de)
DE (4) DE69922732T2 (de)
MY (1) MY125161A (de)

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ATE237888T1 (de) * 1998-10-30 2003-05-15 Broadcom Corp Verallgemeinerter faltungsver- und - entschachteler
JP2000224051A (ja) * 1999-01-22 2000-08-11 Texas Instr Inc <Ti> たたみこみインタ―リ―ビング用の効率的メモリアドレス指定方式
KR100601624B1 (ko) * 1999-10-30 2006-07-14 삼성전자주식회사 인터리버빙과 디인터리빙 장치 및 방법
JP2002076915A (ja) * 2000-08-31 2002-03-15 Sony Corp インターリーブ装置及びインターリーブ方法、並びに、復号装置及び復号方法
US6947491B2 (en) * 2000-09-13 2005-09-20 Interdigital Technology Corporation Third generation FDD modem interleaver
US7770010B2 (en) * 2000-09-18 2010-08-03 Wideband Semiconductors Inc. Dynamically configurable interleaver scheme using at least one dynamically changeable interleaving parameter
US6915479B2 (en) 2001-05-17 2005-07-05 Matsushita Electric Industrial Co., Ltd. Apparatus and method for error correction
KR100414067B1 (ko) * 2001-06-05 2004-01-07 엘지전자 주식회사 인터리브 메모리 제어 장치 및 방법
EP1388947A1 (de) 2002-08-05 2004-02-11 Alcatel System mit Verschachteler und Entschachteler
KR100518295B1 (ko) * 2003-03-14 2005-10-04 삼성전자주식회사 디지털 통신 시스템의 디인터리빙장치 및 그의디인터리빙방법
CN100397787C (zh) * 2004-01-02 2008-06-25 明基电通股份有限公司 区块交错与解交错的编码方法
TWI264653B (en) * 2004-05-19 2006-10-21 Mediatek Inc Method and apparatus for convolutional interleaving/de-interleaving technique
EP1633052A1 (de) * 2004-09-07 2006-03-08 STMicroelectronics N.V. Blocksunverschachtelungssystem
US7529984B2 (en) * 2004-11-16 2009-05-05 Infineon Technologies Ag Seamless change of depth of a general convolutional interleaver during transmission without loss of data
US7716563B2 (en) * 2004-11-30 2010-05-11 Ciena Corporation Method and apparatus for the efficient implementation of a totally general convolutional interleaver in DMT-based xDSL systems
TWI269535B (en) * 2005-09-13 2006-12-21 Sunplus Technology Co Ltd Convolutional interleaving and de-interleaving circuit and method
CN100455001C (zh) * 2005-09-23 2009-01-21 凌阳科技股份有限公司 回旋交错及去交错的电路与方法
US8799750B1 (en) * 2011-05-09 2014-08-05 Xilinx, Inc. Convolutional interleaver for bursty memory access
CN108073549B (zh) * 2016-11-14 2021-04-27 耐能股份有限公司 卷积运算装置及方法
US10784986B2 (en) 2017-02-28 2020-09-22 Intel Corporation Forward error correction mechanism for peripheral component interconnect-express (PCI-e)
CN109460813B (zh) * 2018-09-10 2022-02-15 中国科学院深圳先进技术研究院 卷积神经网络计算的加速方法、装置、设备及存储介质
US10771189B2 (en) 2018-12-18 2020-09-08 Intel Corporation Forward error correction mechanism for data transmission across multi-lane links
US11637657B2 (en) 2019-02-15 2023-04-25 Intel Corporation Low-latency forward error correction for high-speed serial links
US11249837B2 (en) 2019-03-01 2022-02-15 Intel Corporation Flit-based parallel-forward error correction and parity
US10997111B2 (en) 2019-03-01 2021-05-04 Intel Corporation Flit-based packetization
US11296994B2 (en) 2019-05-13 2022-04-05 Intel Corporation Ordered sets for high-speed interconnects
US11740958B2 (en) 2019-11-27 2023-08-29 Intel Corporation Multi-protocol support on common physical layer
CN115515009B (zh) * 2021-06-23 2024-03-15 瑞昱半导体股份有限公司 回旋时间解交错电路及回旋时间解交错电路的操作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US700399A (en) * 1901-04-11 1902-05-20 Paul Bary Process of electrically pulverizing metals.
US3652998A (en) * 1970-03-01 1972-03-28 Codex Corp Interleavers
GB2059723A (en) * 1979-09-19 1981-04-23 Marconi Co Ltd Interleavers for digital data signals
US5042033A (en) 1989-06-05 1991-08-20 Canadian Marconi Corporation RAM-implemented convolutional interleaver
US5210450A (en) * 1990-04-16 1993-05-11 Tektronix, Inc. Active selectable digital delay circuit
KR0123088B1 (ko) * 1993-12-28 1997-12-05 배순훈 메모리를 이용한 길쌈 디인터리버
US5572532A (en) 1993-12-29 1996-11-05 Zenith Electronics Corp. Convolutional interleaver and deinterleaver
US5537420A (en) * 1994-05-04 1996-07-16 General Instrument Corporation Of Delaware Convolutional interleaver with reduced memory requirements and address generator therefor
JPH09102748A (ja) 1995-10-04 1997-04-15 Matsushita Electric Ind Co Ltd インターリーブ回路
US5764649A (en) 1996-03-29 1998-06-09 Amati Communications Corporation Efficient address generation for convolutional interleaving using a minimal amount of memory
JPH1013253A (ja) * 1996-06-24 1998-01-16 Nec Eng Ltd コンボリューショナル・インターリーバ
KR100192797B1 (ko) * 1996-07-01 1999-06-15 전주범 정적 램을 이용한 길쌈인터리버의 구조
US6055277A (en) * 1997-05-29 2000-04-25 Trw Docket No. Communication system for broadcasting to mobile users

Also Published As

Publication number Publication date
DE69922732T2 (de) 2005-12-08
US6411654B1 (en) 2002-06-25
EP0954109A2 (de) 1999-11-03
EP0954109B1 (de) 2004-12-22
KR100330608B1 (ko) 2002-03-29
CN1503483A (zh) 2004-06-09
DE69935357T2 (de) 2007-11-29
DE69922732D1 (de) 2005-01-27
CN100375393C (zh) 2008-03-12
EP1315300B1 (de) 2007-02-28
EP1317069A2 (de) 2003-06-04
DE69935356D1 (de) 2007-04-12
CN100358243C (zh) 2007-12-26
EP0954109A3 (de) 2000-06-14
EP1304810A3 (de) 2004-11-03
EP1304810B1 (de) 2007-02-28
EP1315300A2 (de) 2003-05-28
KR19990083538A (ko) 1999-11-25
EP1317069A3 (de) 2004-10-13
MY125161A (en) 2006-07-31
DE69935358T2 (de) 2007-11-29
EP1304810A2 (de) 2003-04-23
CN1240315A (zh) 2000-01-05
DE69935356T2 (de) 2007-11-08
EP1317069B1 (de) 2007-02-28
EP1315300A3 (de) 2004-10-13
DE69935358D1 (de) 2007-04-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP