DE69914241D1 - Addier- Vergleichs- Auswahl- Schaltung für einen Viterbi Dekodierer - Google Patents

Addier- Vergleichs- Auswahl- Schaltung für einen Viterbi Dekodierer

Info

Publication number
DE69914241D1
DE69914241D1 DE69914241T DE69914241T DE69914241D1 DE 69914241 D1 DE69914241 D1 DE 69914241D1 DE 69914241 T DE69914241 T DE 69914241T DE 69914241 T DE69914241 T DE 69914241T DE 69914241 D1 DE69914241 D1 DE 69914241D1
Authority
DE
Germany
Prior art keywords
compare
add
select circuit
viterbi decoder
viterbi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69914241T
Other languages
English (en)
Other versions
DE69914241T2 (de
Inventor
Sang-Bong Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE69914241D1 publication Critical patent/DE69914241D1/de
Publication of DE69914241T2 publication Critical patent/DE69914241T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
DE69914241T 1998-03-17 1999-03-17 Addier- Vergleichs- Auswahl- Schaltung für einen Viterbi Dekodierer Expired - Fee Related DE69914241T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9805573 1998-03-17
GB9805573A GB2335578B (en) 1998-03-17 1998-03-17 Add-compare selection circuit

Publications (2)

Publication Number Publication Date
DE69914241D1 true DE69914241D1 (de) 2004-02-26
DE69914241T2 DE69914241T2 (de) 2004-11-04

Family

ID=10828638

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69914241T Expired - Fee Related DE69914241T2 (de) 1998-03-17 1999-03-17 Addier- Vergleichs- Auswahl- Schaltung für einen Viterbi Dekodierer

Country Status (6)

Country Link
US (1) US6529557B1 (de)
EP (1) EP0944173B1 (de)
KR (1) KR19990076528A (de)
CN (1) CN1175581C (de)
DE (1) DE69914241T2 (de)
GB (1) GB2335578B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3501725B2 (ja) 2000-05-12 2004-03-02 日本電気株式会社 ビタビ復号器
EP1158683A1 (de) * 2000-05-24 2001-11-28 Infineon Technologies AG Vorrichtung und Verfahren zum Durchführen eines Viterbi-Algorithmus
JP4478119B2 (ja) * 2005-05-25 2010-06-09 パナソニック株式会社 受信装置
KR101581804B1 (ko) * 2009-06-11 2015-12-31 삼성전자주식회사 터보 디코더에서 가산비교선택 과정 수행 장치 및 이를 위한 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233933A (ja) * 1986-04-03 1987-10-14 Toshiba Corp ヴイタビ復号法
US5251233A (en) * 1990-12-20 1993-10-05 Motorola, Inc. Apparatus and method for equalizing a corrupted signal in a receiver
JPH06140951A (ja) * 1992-10-27 1994-05-20 Sony Corp ビタビ等化器
FR2718865B1 (fr) * 1994-04-15 1996-07-19 Texas Instruments France Procédé et dispositif à processeur de signaux numériques pour la mise en Óoeuvre d'un algorithme de Viterbi.
JP3241210B2 (ja) * 1994-06-23 2001-12-25 沖電気工業株式会社 ビタビ復号方法及びビタビ復号回路
US5841819A (en) * 1996-04-09 1998-11-24 Thomson Multimedia, S.A. Viterbi decoder for digital packet signals

Also Published As

Publication number Publication date
GB2335578B (en) 2000-07-12
CN1175581C (zh) 2004-11-10
EP0944173B1 (de) 2004-01-21
US6529557B1 (en) 2003-03-04
GB2335578A (en) 1999-09-22
GB9805573D0 (en) 1998-05-13
EP0944173A3 (de) 2000-02-23
CN1235429A (zh) 1999-11-17
EP0944173A2 (de) 1999-09-22
DE69914241T2 (de) 2004-11-04
KR19990076528A (ko) 1999-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee