DE69903866D1 - Multiplizierer mit niedriger Leistung für CPU und DSP - Google Patents
Multiplizierer mit niedriger Leistung für CPU und DSPInfo
- Publication number
- DE69903866D1 DE69903866D1 DE69903866T DE69903866T DE69903866D1 DE 69903866 D1 DE69903866 D1 DE 69903866D1 DE 69903866 T DE69903866 T DE 69903866T DE 69903866 T DE69903866 T DE 69903866T DE 69903866 D1 DE69903866 D1 DE 69903866D1
- Authority
- DE
- Germany
- Prior art keywords
- dsp
- cpu
- low power
- power multiplier
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Complex Calculations (AREA)
- Advance Control (AREA)
- Power Conversion In General (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/025,945 US6065032A (en) | 1998-02-19 | 1998-02-19 | Low power multiplier for CPU and DSP |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69903866D1 true DE69903866D1 (de) | 2002-12-19 |
DE69903866T2 DE69903866T2 (de) | 2003-09-18 |
Family
ID=21828928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69903866T Expired - Lifetime DE69903866T2 (de) | 1998-02-19 | 1999-02-09 | Multiplizierer mit niedriger Leistung für CPU und DSP |
Country Status (9)
Country | Link |
---|---|
US (2) | US6065032A (de) |
EP (1) | EP0938043B1 (de) |
JP (1) | JPH11272450A (de) |
KR (1) | KR19990072622A (de) |
CN (1) | CN100347666C (de) |
AU (1) | AU1729899A (de) |
BR (1) | BR9900745A (de) |
CA (1) | CA2258358C (de) |
DE (1) | DE69903866T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7203718B1 (en) * | 1999-10-29 | 2007-04-10 | Pentomics, Inc. | Apparatus and method for angle rotation |
US6963889B1 (en) * | 2000-02-24 | 2005-11-08 | Intel Corporation | Wave digital filter with low power consumption |
US6877022B1 (en) * | 2001-02-16 | 2005-04-05 | Texas Instruments Incorporated | Booth encoding circuit for a multiplier of a multiply-accumulate module |
US6901423B1 (en) * | 2001-04-23 | 2005-05-31 | Cirrus Logic, Inc. | Noise invariant circuits, systems and methods |
US7024445B2 (en) * | 2001-12-20 | 2006-04-04 | Analog Devices, Inc. | Method and apparatus for use in booth-encoded multiplication |
US20030158880A1 (en) * | 2002-02-13 | 2003-08-21 | Ng Kenneth Y. | Booth encoder and partial products circuit |
US7069290B2 (en) * | 2002-05-06 | 2006-06-27 | Lucent Technologies Inc. | Power efficient booth recoded multiplier and method of multiplication |
KR100477509B1 (ko) * | 2002-10-02 | 2005-03-17 | 전자부품연구원 | 고속 연산기를 위한 래딕스-4 부스 연산기 |
US7308470B2 (en) * | 2003-12-05 | 2007-12-11 | Intel Corporation | Smaller and lower power static mux circuitry in generating multiplier partial product signals |
KR20050081407A (ko) | 2004-02-13 | 2005-08-19 | 삼성전자주식회사 | 부스 알고리즘을 이용한 곱셈기의 인코더 |
US7358765B2 (en) * | 2005-02-23 | 2008-04-15 | Cswitch Corporation | Dedicated logic cells employing configurable logic and dedicated logic functions |
JP4355705B2 (ja) | 2006-02-23 | 2009-11-04 | エヌイーシーコンピュータテクノ株式会社 | 乗算装置、及び演算装置 |
CN103412737B (zh) * | 2013-06-27 | 2016-08-10 | 清华大学 | 实现基4-Booth编码方法的门电路和基于该方法的流水线大数乘法器 |
CN105808206B (zh) * | 2016-03-04 | 2019-01-08 | 广州海格通信集团股份有限公司 | 基于ram实现乘法运算的方法及其系统 |
CN107977191B (zh) * | 2016-10-21 | 2021-07-27 | 中国科学院微电子研究所 | 一种低功耗并行乘法器 |
CN111738428B (zh) * | 2019-03-25 | 2023-08-25 | 上海寒武纪信息科技有限公司 | 计算装置、方法及相关产品 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4644488A (en) * | 1983-10-12 | 1987-02-17 | California Institute Of Technology | Pipeline active filter utilizing a booth type multiplier |
JPS62229439A (ja) * | 1986-03-31 | 1987-10-08 | Toshiba Corp | 並列乗算器 |
US4817029A (en) * | 1987-05-11 | 1989-03-28 | United Technologies Corporation | Multiple-precision Booth's recode multiplier |
US5040139A (en) * | 1990-04-16 | 1991-08-13 | Tran Dzung J | Transmission gate multiplexer (TGM) logic circuits and multiplier architectures |
US5260898A (en) * | 1992-03-13 | 1993-11-09 | Sun Microsystems, Inc. | Result cache for complex arithmetic units |
US5262973A (en) * | 1992-03-13 | 1993-11-16 | Sun Microsystems, Inc. | Method and apparatus for optimizing complex arithmetic units for trivial operands |
JP2970231B2 (ja) * | 1992-07-02 | 1999-11-02 | 日本電気株式会社 | 並列乗算回路 |
US5734601A (en) * | 1995-01-30 | 1998-03-31 | Cirrus Logic, Inc. | Booth multiplier with low power, high performance input circuitry |
CN1117165A (zh) * | 1995-08-14 | 1996-02-21 | 大宇电子株式会社 | 二进制乘法器中的布斯编码器 |
JPH09101877A (ja) * | 1995-10-06 | 1997-04-15 | Ricoh Co Ltd | 乗算演算方法及び乗算演算装置 |
-
1998
- 1998-02-19 US US09/025,945 patent/US6065032A/en not_active Expired - Lifetime
-
1999
- 1999-01-11 CA CA002258358A patent/CA2258358C/en not_active Expired - Fee Related
- 1999-02-05 BR BR9900745-2A patent/BR9900745A/pt not_active Application Discontinuation
- 1999-02-09 DE DE69903866T patent/DE69903866T2/de not_active Expired - Lifetime
- 1999-02-09 EP EP99300934A patent/EP0938043B1/de not_active Expired - Lifetime
- 1999-02-12 KR KR1019990004956A patent/KR19990072622A/ko not_active Application Discontinuation
- 1999-02-13 CN CNB991023099A patent/CN100347666C/zh not_active Expired - Fee Related
- 1999-02-15 AU AU17298/99A patent/AU1729899A/en not_active Abandoned
- 1999-02-18 JP JP11039705A patent/JPH11272450A/ja active Pending
- 1999-11-02 US US09/431,851 patent/US6275842B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
BR9900745A (pt) | 1999-12-21 |
DE69903866T2 (de) | 2003-09-18 |
CA2258358A1 (en) | 1999-08-19 |
AU1729899A (en) | 1999-09-02 |
EP0938043A2 (de) | 1999-08-25 |
CA2258358C (en) | 2001-10-02 |
CN1227366A (zh) | 1999-09-01 |
EP0938043A3 (de) | 1999-09-29 |
JPH11272450A (ja) | 1999-10-08 |
US6275842B1 (en) | 2001-08-14 |
US6065032A (en) | 2000-05-16 |
CN100347666C (zh) | 2007-11-07 |
KR19990072622A (ko) | 1999-09-27 |
EP0938043B1 (de) | 2002-11-13 |
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