DE69841445D1 - Verfahren zur Abscheidung einer Schicht aus polykristallinem Material über einem Silizium enthaltenden Substrat - Google Patents

Verfahren zur Abscheidung einer Schicht aus polykristallinem Material über einem Silizium enthaltenden Substrat

Info

Publication number
DE69841445D1
DE69841445D1 DE69841445T DE69841445T DE69841445D1 DE 69841445 D1 DE69841445 D1 DE 69841445D1 DE 69841445 T DE69841445 T DE 69841445T DE 69841445 T DE69841445 T DE 69841445T DE 69841445 D1 DE69841445 D1 DE 69841445D1
Authority
DE
Germany
Prior art keywords
depositing
silicon
layer
material over
containing substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841445T
Other languages
English (en)
Inventor
Jorge Luis Regolini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chartoleaux KG LLC
Original Assignee
Chartoleaux KG LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartoleaux KG LLC filed Critical Chartoleaux KG LLC
Application granted granted Critical
Publication of DE69841445D1 publication Critical patent/DE69841445D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69841445T 1997-06-13 1998-06-09 Verfahren zur Abscheidung einer Schicht aus polykristallinem Material über einem Silizium enthaltenden Substrat Expired - Lifetime DE69841445D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9707348A FR2764732B1 (fr) 1997-06-13 1997-06-13 Procede de depot d'une couche d'un materiau polycristallin sur un substrat a base de silicium

Publications (1)

Publication Number Publication Date
DE69841445D1 true DE69841445D1 (de) 2010-03-04

Family

ID=9507943

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841445T Expired - Lifetime DE69841445D1 (de) 1997-06-13 1998-06-09 Verfahren zur Abscheidung einer Schicht aus polykristallinem Material über einem Silizium enthaltenden Substrat

Country Status (4)

Country Link
EP (1) EP0884770B1 (de)
JP (1) JPH1180962A (de)
DE (1) DE69841445D1 (de)
FR (1) FR2764732B1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6207483B1 (en) * 2000-03-17 2001-03-27 Taiwan Semiconductor Manufacturing Company Method for smoothing polysilicon gate structures in CMOS devices
TW550648B (en) 2001-07-02 2003-09-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
WO2008047728A1 (fr) * 2006-10-13 2008-04-24 National Institute Of Advanced Industrial Science And Technology Stratifié, matériaux de meulage et abrasif réalisés à l'aide de celui-ci, et procédé pour la formation du stratifié
JP5182852B2 (ja) * 2007-10-12 2013-04-17 独立行政法人産業技術総合研究所 炭化珪素の研磨剤、及びそれを用いた炭化珪素の研磨方法
JP5439785B2 (ja) * 2008-09-30 2014-03-12 大日本印刷株式会社 ゲルマニウム蒸着シート
KR102601607B1 (ko) * 2018-10-01 2023-11-13 삼성전자주식회사 그래핀의 형성방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4540607A (en) * 1983-08-08 1985-09-10 Gould, Inc. Selective LPCVD tungsten deposition by the silicon reduction method
GB2214708A (en) * 1988-01-20 1989-09-06 Philips Nv A method of manufacturing a semiconductor device

Also Published As

Publication number Publication date
FR2764732A1 (fr) 1998-12-18
FR2764732B1 (fr) 1999-09-17
EP0884770B1 (de) 2010-01-13
JPH1180962A (ja) 1999-03-26
EP0884770A1 (de) 1998-12-16

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Legal Events

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