DE69832836D1 - Arbitrierungssteuerungsgerät auf einem Mehrpunkt-Hochgeschindigkeits-Serienbus - Google Patents

Arbitrierungssteuerungsgerät auf einem Mehrpunkt-Hochgeschindigkeits-Serienbus

Info

Publication number
DE69832836D1
DE69832836D1 DE69832836T DE69832836T DE69832836D1 DE 69832836 D1 DE69832836 D1 DE 69832836D1 DE 69832836 T DE69832836 T DE 69832836T DE 69832836 T DE69832836 T DE 69832836T DE 69832836 D1 DE69832836 D1 DE 69832836D1
Authority
DE
Germany
Prior art keywords
control device
high speed
serial bus
speed serial
arbitration control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69832836T
Other languages
English (en)
Other versions
DE69832836T2 (de
Inventor
Eamonn Gormley
James M Hite
Chad A Pralle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Clearwire Corp
Original Assignee
Clearwire Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clearwire Corp filed Critical Clearwire Corp
Publication of DE69832836D1 publication Critical patent/DE69832836D1/de
Application granted granted Critical
Publication of DE69832836T2 publication Critical patent/DE69832836T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40052—High-speed IEEE 1394 serial bus
    • H04L12/40084—Bus arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
DE69832836T 1997-03-26 1998-03-18 Arbitrierungssteuerungsgerät auf einem Mehrpunkt-Hochgeschindigkeits-Serienbus Expired - Lifetime DE69832836T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/824,937 US5859985A (en) 1996-01-14 1997-03-26 Arbitration controller for providing arbitration on a multipoint high speed serial bus using drivers having output enable pins
US824937 1997-03-26

Publications (2)

Publication Number Publication Date
DE69832836D1 true DE69832836D1 (de) 2006-01-26
DE69832836T2 DE69832836T2 (de) 2006-09-14

Family

ID=25242702

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69832836T Expired - Lifetime DE69832836T2 (de) 1997-03-26 1998-03-18 Arbitrierungssteuerungsgerät auf einem Mehrpunkt-Hochgeschindigkeits-Serienbus

Country Status (5)

Country Link
US (1) US5859985A (de)
EP (1) EP0867813B1 (de)
JP (1) JP3309072B2 (de)
CA (1) CA2228708C (de)
DE (1) DE69832836T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6601124B1 (en) 2000-02-14 2003-07-29 International Business Machines Corporation Universal interface for selectively coupling to a computer port type and method therefor
US20020056113A1 (en) * 2000-07-04 2002-05-09 Ulan Co., Ltd. Home network connection system
US6766360B1 (en) 2000-07-14 2004-07-20 Fujitsu Limited Caching mechanism for remote read-only data in a cache coherent non-uniform memory access (CCNUMA) architecture
JP3575419B2 (ja) * 2000-10-24 2004-10-13 日本電気株式会社 装置状態制御回路、及び装置状態制御方法
US6754776B2 (en) 2001-05-17 2004-06-22 Fujitsu Limited Method and system for logical partitioning of cache memory structures in a partitoned computer system
US7380001B2 (en) * 2001-05-17 2008-05-27 Fujitsu Limited Fault containment and error handling in a partitioned system with shared resources
US6961761B2 (en) * 2001-05-17 2005-11-01 Fujitsu Limited System and method for partitioning a computer system into domains
JP3672845B2 (ja) * 2001-05-25 2005-07-20 シャープ株式会社 インターフェース装置及びこれを備えた通信機器並びに通信方法
US6862634B2 (en) * 2001-06-29 2005-03-01 Fujitsu Limited Mechanism to improve performance in a multi-node computer system
US6877054B2 (en) * 2001-07-16 2005-04-05 Rambus Inc. Method and apparatus for position dependent data scheduling
EP3614273A3 (de) 2012-12-13 2020-04-15 Coherent Logix, Incorporated Multiprozessorsystem mit verbessertem sekundärem verbindungsnetzwerk
EP3499806B1 (de) * 2017-12-13 2020-08-05 Nxp B.V. Knoten und verfahren zur durchführung von messungen und signalanalysen auf einem multi-master-zugangsbus

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5005151A (en) * 1988-05-13 1991-04-02 Dallas Semiconductor Corporation Interleaved arbitration scheme for interfacing parallel and serial ports to a parallel system port
US5276887A (en) * 1991-06-06 1994-01-04 Commodore Electronics Limited Bus arbitration system for granting bus access to devices following two-wire bus arbitration protocol and devices following three-wire bus arbitration protocol
EP0527015A2 (de) * 1991-08-06 1993-02-10 AT&T Corp. Signalisierung mit geringem Leistungsverbrauch unter Verwendung einer Verzögerung für das Umschalten der Ausgangsimpedanz
US5509126A (en) * 1993-03-16 1996-04-16 Apple Computer, Inc. Method and apparatus for a dynamic, multi-speed bus architecture having a scalable interface
US5493657A (en) * 1993-06-21 1996-02-20 Apple Computer, Inc. High speed dominant mode bus for differential signals
US5611053A (en) * 1994-01-21 1997-03-11 Advanced Micro Devices, Inc. Apparatus and method for integrating bus master ownership of local bus load by plural data transceivers
AU1689795A (en) * 1994-01-25 1995-08-08 Apple Computer, Inc. Improved bus protocol using separate clocks for arbitration and data transfer

Also Published As

Publication number Publication date
EP0867813B1 (de) 2005-12-21
JP3309072B2 (ja) 2002-07-29
CA2228708C (en) 2001-10-30
EP0867813A3 (de) 2001-05-23
DE69832836T2 (de) 2006-09-14
CA2228708A1 (en) 1998-09-26
US5859985A (en) 1999-01-12
JPH10307658A (ja) 1998-11-17
EP0867813A2 (de) 1998-09-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition