DE69816883D1 - Verarbeitungsschaltung für Synchronisierungssignal - Google Patents
Verarbeitungsschaltung für SynchronisierungssignalInfo
- Publication number
- DE69816883D1 DE69816883D1 DE69816883T DE69816883T DE69816883D1 DE 69816883 D1 DE69816883 D1 DE 69816883D1 DE 69816883 T DE69816883 T DE 69816883T DE 69816883 T DE69816883 T DE 69816883T DE 69816883 D1 DE69816883 D1 DE 69816883D1
- Authority
- DE
- Germany
- Prior art keywords
- processing circuit
- synchronization signal
- synchronization
- signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Controls And Circuits For Display Device (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03161497A JP3555372B2 (ja) | 1997-02-17 | 1997-02-17 | 同期処理回路 |
JP3161497 | 1997-02-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69816883D1 true DE69816883D1 (de) | 2003-09-11 |
DE69816883T2 DE69816883T2 (de) | 2004-07-08 |
Family
ID=12336098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69816883T Expired - Lifetime DE69816883T2 (de) | 1997-02-17 | 1998-02-17 | Verarbeitungsschaltung für Synchronisierungssignal |
Country Status (7)
Country | Link |
---|---|
US (1) | US6172711B1 (de) |
EP (1) | EP0859470B1 (de) |
JP (1) | JP3555372B2 (de) |
KR (1) | KR100267038B1 (de) |
CN (1) | CN1209930C (de) |
CA (1) | CA2229765C (de) |
DE (1) | DE69816883T2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001094823A (ja) * | 1999-09-22 | 2001-04-06 | Sony Corp | マルチスキャン対応水平同期信号生成システム |
KR100429993B1 (ko) * | 2001-09-12 | 2004-05-03 | 엘지전자 주식회사 | 영상처리기의 시스템클럭신호 보상 방법 및 장치 |
CN100376929C (zh) * | 2005-04-07 | 2008-03-26 | 鸿富锦精密工业(深圳)有限公司 | 视频图形阵列彩色信号发生器 |
CN100573360C (zh) * | 2005-04-25 | 2009-12-23 | 佳能株式会社 | 成像设备 |
US7688928B2 (en) * | 2006-09-05 | 2010-03-30 | Lsi Corporation | Duty cycle counting phase calibration scheme of an input/output (I/O) interface |
RU2517269C2 (ru) * | 2012-03-20 | 2014-05-27 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" | Устройство тактовой синхронизации для преобразования прерывистой информации в непрерывную |
US11063800B2 (en) * | 2017-04-04 | 2021-07-13 | Qualcomm Incorporated | Synchronization signaling supporting multiple waveforms |
CN107769772B (zh) * | 2017-11-02 | 2023-09-01 | 中国科学院西安光学精密机械研究所 | 一种低晃动同步扫描电路系统 |
US10505524B1 (en) * | 2019-03-06 | 2019-12-10 | Quantum Machines | Synchronization in a quantum controller with modular and dynamic pulse generation and routing |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4498103A (en) * | 1982-09-13 | 1985-02-05 | Rca Corporation | Slow genlock circuit |
JPH0832059B2 (ja) * | 1987-03-09 | 1996-03-27 | 株式会社日立製作所 | ディジタルテレビジョン信号処理装置 |
JPH06334894A (ja) * | 1993-05-19 | 1994-12-02 | Toshiba Corp | 水平同期装置 |
-
1997
- 1997-02-17 JP JP03161497A patent/JP3555372B2/ja not_active Expired - Fee Related
-
1998
- 1998-02-17 DE DE69816883T patent/DE69816883T2/de not_active Expired - Lifetime
- 1998-02-17 KR KR1019980004781A patent/KR100267038B1/ko not_active IP Right Cessation
- 1998-02-17 EP EP98102685A patent/EP0859470B1/de not_active Expired - Lifetime
- 1998-02-17 US US09/024,477 patent/US6172711B1/en not_active Expired - Fee Related
- 1998-02-17 CN CNB981052169A patent/CN1209930C/zh not_active Expired - Fee Related
- 1998-02-17 CA CA002229765A patent/CA2229765C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69816883T2 (de) | 2004-07-08 |
EP0859470B1 (de) | 2003-08-06 |
JP3555372B2 (ja) | 2004-08-18 |
KR19980071420A (ko) | 1998-10-26 |
CA2229765C (en) | 2003-04-29 |
KR100267038B1 (ko) | 2000-09-15 |
CA2229765A1 (en) | 1998-08-17 |
JPH10229504A (ja) | 1998-08-25 |
EP0859470A1 (de) | 1998-08-19 |
CN1194545A (zh) | 1998-09-30 |
US6172711B1 (en) | 2001-01-09 |
CN1209930C (zh) | 2005-07-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORP., KADOMA, OSAKA, JP |