DE69804562D1 - Prozessarchitektur und Verfahren zur Durchführung von verschiedenen Adressierungsarten - Google Patents

Prozessarchitektur und Verfahren zur Durchführung von verschiedenen Adressierungsarten

Info

Publication number
DE69804562D1
DE69804562D1 DE69804562T DE69804562T DE69804562D1 DE 69804562 D1 DE69804562 D1 DE 69804562D1 DE 69804562 T DE69804562 T DE 69804562T DE 69804562 T DE69804562 T DE 69804562T DE 69804562 D1 DE69804562 D1 DE 69804562D1
Authority
DE
Germany
Prior art keywords
indirect addressing
addressing
procedures
carrying
different types
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69804562T
Other languages
English (en)
Other versions
DE69804562T2 (de
Inventor
Sumit K Mitra
Joseph W Triece
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of DE69804562D1 publication Critical patent/DE69804562D1/de
Application granted granted Critical
Publication of DE69804562T2 publication Critical patent/DE69804562T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
DE69804562T 1997-10-07 1998-09-28 Prozessarchitektur und Verfahren zur Durchführung von verschiedenen Adressierungsarten Expired - Lifetime DE69804562T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/946,426 US6192463B1 (en) 1997-10-07 1997-10-07 Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor

Publications (2)

Publication Number Publication Date
DE69804562D1 true DE69804562D1 (de) 2002-05-08
DE69804562T2 DE69804562T2 (de) 2002-11-21

Family

ID=25484456

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69804562T Expired - Lifetime DE69804562T2 (de) 1997-10-07 1998-09-28 Prozessarchitektur und Verfahren zur Durchführung von verschiedenen Adressierungsarten

Country Status (7)

Country Link
US (2) US6192463B1 (de)
EP (1) EP0908812B1 (de)
JP (1) JPH11224193A (de)
KR (1) KR19990036893A (de)
AT (1) ATE215713T1 (de)
DE (1) DE69804562T2 (de)
TW (1) TW405075B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6192463B1 (en) * 1997-10-07 2001-02-20 Microchip Technology, Inc. Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
US6560698B1 (en) * 1999-05-07 2003-05-06 Advanced Micro Devices, Inc. Register change summary resource
US20040030963A1 (en) * 2002-08-12 2004-02-12 Sun Microsystems, Inc., A Delaware Corporation Method and apparatus for debugging computer program
US7437532B1 (en) * 2003-05-07 2008-10-14 Marvell International Ltd. Memory mapped register file
EP1706817B1 (de) 2003-10-23 2015-04-15 Microchip Technology Inc. Mikrosteuerung mit einer virtuellen speicherbank
US20050172064A1 (en) * 2004-01-29 2005-08-04 Marcelo Krygier Method and apparatus for addressing in mass storage non-volatile memory devices
US20070266225A1 (en) * 2006-05-09 2007-11-15 Ko Tak K V Microcontroller unit
US7908458B2 (en) * 2007-11-21 2011-03-15 Microchip Technology Incorporated Ethernet controller
US8004988B2 (en) * 2007-11-21 2011-08-23 Microchip Technology Incorporated Ethernet controller
US8539210B2 (en) * 2007-11-30 2013-09-17 Microchip Technology Incorporated Context switching with automatic saving of special function registers memory-mapped to all banks
US7996651B2 (en) * 2007-11-30 2011-08-09 Microchip Technology Incorporated Enhanced microprocessor or microcontroller
US8209521B2 (en) 2008-10-18 2012-06-26 Micron Technology, Inc. Methods of indirect register access including automatic modification of a directly accessible address register
US8938590B2 (en) * 2008-10-18 2015-01-20 Micron Technology, Inc. Indirect register access method and system
US8402249B1 (en) * 2009-10-19 2013-03-19 Marvell International Ltd. System and method for mixed-mode SDRAM address mapping
GB2540948B (en) * 2015-07-31 2021-09-15 Advanced Risc Mach Ltd Apparatus with reduced hardware register set

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4047245A (en) 1976-07-12 1977-09-06 Western Electric Company, Incorporated Indirect memory addressing
US4240142A (en) 1978-12-29 1980-12-16 Bell Telephone Laboratories, Incorporated Data processing apparatus providing autoincrementing of memory pointer registers
US5142633A (en) 1989-02-03 1992-08-25 Digital Equipment Corporation Preprocessing implied specifiers in a pipelined processor
JPH02266421A (ja) * 1989-04-07 1990-10-31 Ricoh Co Ltd 画像形成装置
US5381537A (en) * 1991-12-06 1995-01-10 International Business Machines Corporation Large logical addressing method and means
JPH08180001A (ja) * 1994-04-12 1996-07-12 Mitsubishi Electric Corp 通信方式及び通信方法及びネットワークインタフェース
US5715418A (en) * 1994-07-27 1998-02-03 Seagate Technologies, Inc. Autonomous high speed linear space address mode translation for use with a computer hard disc system
US5568651A (en) * 1994-11-03 1996-10-22 Digital Equipment Corporation Method for detection of configuration types and addressing modes of a dynamic RAM
JP3451595B2 (ja) * 1995-06-07 2003-09-29 インターナショナル・ビジネス・マシーンズ・コーポレーション 二つの別個の命令セット・アーキテクチャへの拡張をサポートすることができるアーキテクチャ・モード制御を備えたマイクロプロセッサ
US5860155A (en) 1995-11-16 1999-01-12 Utek Semiconductor Corporation Instruction decoding mechanism for reducing execution time by earlier detection and replacement of indirect addresses with direct addresses
US5835970A (en) * 1995-12-21 1998-11-10 Cypress Semiconductor Corp. Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
US5809546A (en) * 1996-05-23 1998-09-15 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for controlling accesses to the buffers
US5978836A (en) * 1997-07-28 1999-11-02 Solectron Corporation Workflow systems and methods
US6192463B1 (en) * 1997-10-07 2001-02-20 Microchip Technology, Inc. Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
US6128727A (en) * 1998-08-21 2000-10-03 Advanced Micro Devices, Inc. Self modifying code to test all possible addressing modes

Also Published As

Publication number Publication date
ATE215713T1 (de) 2002-04-15
JPH11224193A (ja) 1999-08-17
US6578139B1 (en) 2003-06-10
DE69804562T2 (de) 2002-11-21
TW405075B (en) 2000-09-11
EP0908812A3 (de) 1999-12-08
KR19990036893A (ko) 1999-05-25
EP0908812B1 (de) 2002-04-03
US6192463B1 (en) 2001-02-20
EP0908812A2 (de) 1999-04-14

Similar Documents

Publication Publication Date Title
DE69804562T2 (de) Prozessarchitektur und Verfahren zur Durchführung von verschiedenen Adressierungsarten
CA1261479A (en) Direct input/output in a virtual memory system
EP0331900A3 (de) Verfahren und Vorrichtung für Zugriffsrechtensteuerung
DE69227465T2 (de) Cpu mit pipeline-einheit und effektiv-adressenrechnungseinheit mit möglichkeit zur beibehaltung von virtuellen operandenadressen.
DE69724352D1 (de) Zusatz-Adressenübersetzungspuffer zur Unterstützung von Datenzugriffen in entfernten Adressenräumen
DE69718679T2 (de) System zur kontrolle des zugriffes auf ein register abgebildet auf einen e/a addressbereich eines rechnersystems
JPS6436336A (en) Calculator system
KR910012962A (ko) Dma제어기
TW375706B (en) Programmable memory access
PT71826B (en) Data processing system including internal register adressing arrangements
EP0918279A3 (de) Prozessorarchitekturschema mit mehreren Quellen zur Bereitstellung von Bankadressenwerten
KR970071281A (ko) 인터리브 캐시메모리 및 그 운영방법과 데이터 처리 시스템
DE69807412T2 (de) Prozessorarchitekturschema und Befehlssatz zur Maximierung verfügbarer Opcodes und zum Einsetzen verschiedener Adressierungsmodi
SE7906180L (sv) Anordning for omvandling av virtuella adresser till reella adresser
DE69808020T2 (de) Adressengenerator und Verfahren zur indirekten Adressierung in einem einzigen Zyklus
JPS5613576A (en) Memory access control system
GB2009982A (en) Replacement location selection in cache memory
WO1996008767A3 (en) Microcontroller system with a multiple-register stacking instruction
ATE105099T1 (de) Integrierte schaltung zur dynamischen programmierung.
RU96118308A (ru) Устройство параллельного обращения к общей памяти
JPH04280331A (ja) 読み出し専用リストアクセス方式
JPS54124644A (en) Data transfer system
JPS6488672A (en) Multiprocessor system
DE68926837T2 (de) Einrichtung und Verfahren zur verbesserten Umsetzung von virtueller zu realer Adresse für Cache-Speicherzugriff
SE8001206L (sv) Anordning vid datorutrustning, foretredesvis mikrodatorutrustning

Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: DF-MP, 80333 MUENCHEN