DE69802426D1 - Taktschema für digitales signalprozessorsystem - Google Patents
Taktschema für digitales signalprozessorsystemInfo
- Publication number
- DE69802426D1 DE69802426D1 DE69802426T DE69802426T DE69802426D1 DE 69802426 D1 DE69802426 D1 DE 69802426D1 DE 69802426 T DE69802426 T DE 69802426T DE 69802426 T DE69802426 T DE 69802426T DE 69802426 D1 DE69802426 D1 DE 69802426D1
- Authority
- DE
- Germany
- Prior art keywords
- digital signal
- signal processor
- processor system
- cycle diagram
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/931,665 US5922076A (en) | 1997-09-16 | 1997-09-16 | Clocking scheme for digital signal processor system |
PCT/US1998/019277 WO1999014683A1 (en) | 1997-09-16 | 1998-09-16 | Clocking scheme for digital signal processor system |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69802426D1 true DE69802426D1 (de) | 2001-12-13 |
DE69802426T2 DE69802426T2 (de) | 2002-11-07 |
Family
ID=25461155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69802426T Expired - Lifetime DE69802426T2 (de) | 1997-09-16 | 1998-09-16 | Taktschema für digitales signalprozessorsystem |
Country Status (5)
Country | Link |
---|---|
US (1) | US5922076A (de) |
EP (1) | EP1015992B1 (de) |
JP (1) | JP4303417B2 (de) |
DE (1) | DE69802426T2 (de) |
WO (1) | WO1999014683A1 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6480548B1 (en) | 1997-11-17 | 2002-11-12 | Silicon Graphics, Inc. | Spacial derivative bus encoder and decoder |
US6775339B1 (en) | 1999-08-27 | 2004-08-10 | Silicon Graphics, Inc. | Circuit design for high-speed digital communication |
US7031420B1 (en) * | 1999-12-30 | 2006-04-18 | Silicon Graphics, Inc. | System and method for adaptively deskewing parallel data signals relative to a clock |
US6417713B1 (en) | 1999-12-30 | 2002-07-09 | Silicon Graphics, Inc. | Programmable differential delay circuit with fine delay adjustment |
US6272070B1 (en) * | 2000-02-09 | 2001-08-07 | Micron Technology, Inc. | Method and apparatus for setting write latency |
US6756827B2 (en) * | 2002-09-11 | 2004-06-29 | Broadcom Corporation | Clock multiplier using masked control of clock pulses |
US7010713B2 (en) | 2002-12-19 | 2006-03-07 | Mosaid Technologies, Inc. | Synchronization circuit and method with transparent latches |
JP2004303195A (ja) * | 2003-03-19 | 2004-10-28 | Seiko Epson Corp | シートコンピュータ、ウェアラブルコンピュータ、ディスプレイ装置及びこれらの製造方法並びに電子機器 |
US7114069B2 (en) | 2003-04-22 | 2006-09-26 | Motorola, Inc. | Reconfigurable processing circuit including a delay locked loop multiple frequency generator for generating a plurality of clock signals which are configured in frequency by a control processor |
US7031372B2 (en) * | 2003-04-22 | 2006-04-18 | Motorola, Inc. | Multiple user reconfigurable CDMA processor |
US7254208B2 (en) | 2003-05-20 | 2007-08-07 | Motorola, Inc. | Delay line based multiple frequency generator circuits for CDMA processing |
JP5448795B2 (ja) | 2009-12-25 | 2014-03-19 | キヤノン株式会社 | 情報処理装置又は情報処理方法 |
JP5377275B2 (ja) * | 2009-12-25 | 2013-12-25 | キヤノン株式会社 | 情報処理装置又は情報処理方法 |
JP7207138B2 (ja) | 2018-10-02 | 2023-01-18 | 株式会社リコー | 生体情報計測システムおよび生体情報計測用プログラム |
CN113472442B (zh) * | 2020-03-31 | 2022-07-01 | 烽火通信科技股份有限公司 | 一种相干dsp芯片的时钟处理方法及系统 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0545581B1 (de) * | 1991-12-06 | 1999-04-21 | National Semiconductor Corporation | Integriertes Datenverarbeitungssystem mit CPU-Kern und unabhängigem parallelen, digitalen Signalprozessormodul |
US5619720A (en) * | 1994-10-04 | 1997-04-08 | Analog Devices, Inc. | Digital signal processor having link ports for point-to-point communication |
US5685005A (en) * | 1994-10-04 | 1997-11-04 | Analog Devices, Inc. | Digital signal processor configured for multiprocessing |
US5611075A (en) * | 1994-10-04 | 1997-03-11 | Analog Devices, Inc. | Bus architecture for digital signal processor allowing time multiplexed access to memory banks |
-
1997
- 1997-09-16 US US08/931,665 patent/US5922076A/en not_active Expired - Lifetime
-
1998
- 1998-09-16 JP JP2000512150A patent/JP4303417B2/ja not_active Expired - Lifetime
- 1998-09-16 DE DE69802426T patent/DE69802426T2/de not_active Expired - Lifetime
- 1998-09-16 WO PCT/US1998/019277 patent/WO1999014683A1/en active IP Right Grant
- 1998-09-16 EP EP98947056A patent/EP1015992B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69802426T2 (de) | 2002-11-07 |
EP1015992B1 (de) | 2001-11-07 |
JP4303417B2 (ja) | 2009-07-29 |
US5922076A (en) | 1999-07-13 |
EP1015992A1 (de) | 2000-07-05 |
WO1999014683A1 (en) | 1999-03-25 |
JP2001516926A (ja) | 2001-10-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de | ||
8370 | Indication of lapse of patent is to be deleted | ||
8364 | No opposition during term of opposition |