DE69719123T2 - System zur Datenverarbeitung und -kommunikation mit PCI-Hochdurchsatzbus - Google Patents

System zur Datenverarbeitung und -kommunikation mit PCI-Hochdurchsatzbus

Info

Publication number
DE69719123T2
DE69719123T2 DE69719123T DE69719123T DE69719123T2 DE 69719123 T2 DE69719123 T2 DE 69719123T2 DE 69719123 T DE69719123 T DE 69719123T DE 69719123 T DE69719123 T DE 69719123T DE 69719123 T2 DE69719123 T2 DE 69719123T2
Authority
DE
Germany
Prior art keywords
communication
data processing
high throughput
pci high
throughput bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69719123T
Other languages
English (en)
Other versions
DE69719123D1 (de
Inventor
Masao Manabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69719123D1 publication Critical patent/DE69719123D1/de
Publication of DE69719123T2 publication Critical patent/DE69719123T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
DE69719123T 1996-07-22 1997-07-17 System zur Datenverarbeitung und -kommunikation mit PCI-Hochdurchsatzbus Expired - Fee Related DE69719123T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8192152A JP2996179B2 (ja) 1996-07-22 1996-07-22 Ｐｃｉバス・システム

Publications (2)

Publication Number Publication Date
DE69719123D1 DE69719123D1 (de) 2003-03-27
DE69719123T2 true DE69719123T2 (de) 2003-11-27

Family

ID=16286571

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69719123T Expired - Fee Related DE69719123T2 (de) 1996-07-22 1997-07-17 System zur Datenverarbeitung und -kommunikation mit PCI-Hochdurchsatzbus

Country Status (6)

Country Link
US (1) US5958032A (de)
EP (1) EP0821311B1 (de)
JP (1) JP2996179B2 (de)
KR (1) KR100230902B1 (de)
DE (1) DE69719123T2 (de)
TW (1) TW382168B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2996179B2 (ja) * 1996-07-22 1999-12-27 日本電気株式会社 Ｐｃｉバス・システム
US6882651B1 (en) * 1998-12-02 2005-04-19 Nortel Networks Limited Flow control of data units across a bus bridge and inter-bus communication system employing same
US6209054B1 (en) * 1998-12-15 2001-03-27 Cisco Technology, Inc. Reliable interrupt reception over buffered bus
US6725312B1 (en) 2000-11-02 2004-04-20 Cml Versatel Inc. Bus architecture for high reliability communications in computer system
JP3870717B2 (ja) * 2001-05-14 2007-01-24 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US7124214B2 (en) * 2003-03-28 2006-10-17 Via Technologies Inc. Method and related apparatus for controlling a peripheral device to transfer data to a bus
CN102411553B (zh) * 2011-08-01 2014-04-30 北京航空航天大学 基于cpci总线的1553b协议数据通信及串行加载模块
DE112011105853B4 (de) * 2011-11-15 2024-04-25 Intel Corporation Verwaltung der Steuerung des Pufferzulaufs durch den Verbindungsstatus
CN103346931B (zh) * 2013-07-10 2016-01-13 北京航天自动控制研究所 一种1553b总线监听系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768548A (en) * 1992-04-15 1998-06-16 Intel Corporation Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
JPH06139186A (ja) * 1992-10-23 1994-05-20 Mitsubishi Electric Corp バス制御方式
US5631906A (en) * 1993-03-11 1997-05-20 Liu; Zheng Medium access control protocol for single bus fair access local area network
JPH07121474A (ja) * 1993-10-21 1995-05-12 Ricoh Co Ltd 情報処理装置
US5613075A (en) * 1993-11-12 1997-03-18 Intel Corporation Method and apparatus for providing deterministic read access to main memory in a computer system
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5594882A (en) * 1995-01-04 1997-01-14 Intel Corporation PCI split transactions utilizing dual address cycle
JP2996179B2 (ja) * 1996-07-22 1999-12-27 日本電気株式会社 Ｐｃｉバス・システム

Also Published As

Publication number Publication date
EP0821311A3 (de) 2002-03-20
US5958032A (en) 1999-09-28
KR980013132A (ko) 1998-04-30
JPH1040215A (ja) 1998-02-13
JP2996179B2 (ja) 1999-12-27
KR100230902B1 (ko) 1999-11-15
EP0821311A2 (de) 1998-01-28
TW382168B (en) 2000-02-11
EP0821311B1 (de) 2003-02-19
DE69719123D1 (de) 2003-03-27

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee