DE69717401D1 - Schaltung und Verfahren zum Erzeugen von Taktsignalen - Google Patents

Schaltung und Verfahren zum Erzeugen von Taktsignalen

Info

Publication number
DE69717401D1
DE69717401D1 DE69717401T DE69717401T DE69717401D1 DE 69717401 D1 DE69717401 D1 DE 69717401D1 DE 69717401 T DE69717401 T DE 69717401T DE 69717401 T DE69717401 T DE 69717401T DE 69717401 D1 DE69717401 D1 DE 69717401D1
Authority
DE
Germany
Prior art keywords
circuit
clock signals
generating clock
generating
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69717401T
Other languages
English (en)
Other versions
DE69717401T2 (de
Inventor
Jason A T Jones
Gary L Swoboda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69717401D1 publication Critical patent/DE69717401D1/de
Publication of DE69717401T2 publication Critical patent/DE69717401T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69717401T 1996-12-09 1997-12-05 Schaltung und Verfahren zum Erzeugen von Taktsignalen Expired - Lifetime DE69717401T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/762,169 US5952863A (en) 1996-12-09 1996-12-09 Circuit and method for generating non-overlapping clock signals for an integrated circuit

Publications (2)

Publication Number Publication Date
DE69717401D1 true DE69717401D1 (de) 2003-01-09
DE69717401T2 DE69717401T2 (de) 2003-08-14

Family

ID=25064301

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69717401T Expired - Lifetime DE69717401T2 (de) 1996-12-09 1997-12-05 Schaltung und Verfahren zum Erzeugen von Taktsignalen

Country Status (4)

Country Link
US (1) US5952863A (de)
EP (1) EP0847140B1 (de)
JP (1) JPH10242820A (de)
DE (1) DE69717401T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6381704B1 (en) * 1998-01-29 2002-04-30 Texas Instruments Incorporated Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor
US6418387B1 (en) * 1999-06-28 2002-07-09 Ltx Corporation Method of and system for generating a binary shmoo plot in N-dimensional space
US6333872B1 (en) 2000-11-06 2001-12-25 International Business Machines Corporation Self-test method for testing read stability in a dual-port SRAM cell
US6452426B1 (en) * 2001-04-16 2002-09-17 Nagesh Tamarapalli Circuit for switching between multiple clocks
US6925616B2 (en) * 2002-10-04 2005-08-02 Sun Microsystems, Inc. Method to test power distribution system
KR100526350B1 (ko) * 2003-08-23 2005-11-08 삼성전자주식회사 다상 클록신호 발생회로 및 방법
US7271626B1 (en) 2004-10-27 2007-09-18 National Semiconductor Corporation Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter
US8934998B1 (en) * 2010-09-11 2015-01-13 Unist, Inc. Method and apparatus for delivery of minimum quantity lubrication

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660767A (en) * 1969-12-18 1972-05-02 Matsushita Electric Ind Co Ltd Frequency divider circuit system
JPS5022593B1 (de) * 1970-06-15 1975-07-31
US3863161A (en) * 1973-11-28 1975-01-28 Rockwell International Corp Digital method and apparatus for dynamically monitoring the frequency of a frequency varying signal
US4109209A (en) * 1977-03-07 1978-08-22 Rca Corporation Pulse staggering circuit
JPS56118125A (en) * 1980-02-25 1981-09-17 Hitachi Ltd Clock and pulse distributor
JPS5813046A (ja) * 1981-07-17 1983-01-25 Victor Co Of Japan Ltd デ−タ読み取り回路
JPS6074745A (ja) * 1983-09-30 1985-04-27 Hitachi Ltd タイミング抽出回路
US4645947A (en) * 1985-12-17 1987-02-24 Intel Corporation Clock driver circuit
US4882505A (en) * 1986-03-24 1989-11-21 International Business Machines Corporation Fully synchronous half-frequency clock generator
US4695873A (en) * 1986-06-10 1987-09-22 Ampex Corporation Horizontal line data position and burst phase encoding apparatus and method
JPS6386414A (ja) * 1986-09-30 1988-04-16 太陽誘電株式会社 積層形セラミツクコンデンサ
US4816700A (en) * 1987-12-16 1989-03-28 Intel Corporation Two-phase non-overlapping clock generator
JPH01256811A (ja) * 1988-04-07 1989-10-13 Nec Corp クロックジェネレータ
US5005193A (en) * 1989-06-29 1991-04-02 Texas Instruments Incorporated Clock pulse generating circuits
JP2740769B2 (ja) * 1990-08-23 1998-04-15 株式会社東芝 可変分周回路
US5341031A (en) * 1990-08-27 1994-08-23 Mitsubishi Denki Kabushiki Kaisha Stable high speed clock generator
JP2721931B2 (ja) * 1990-09-28 1998-03-04 三菱電機株式会社 半導体メモリのためのシリアル選択回路
US5444405A (en) * 1992-03-02 1995-08-22 Seiko Epson Corporation Clock generator with programmable non-overlapping clock edge capability
JP3333248B2 (ja) * 1992-11-10 2002-10-15 株式会社東芝 デューティ検出回路
JPH06318123A (ja) * 1993-05-07 1994-11-15 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5357204A (en) * 1993-09-01 1994-10-18 Intel Corporation One-shot clock generator circuit
JP2959372B2 (ja) * 1993-12-03 1999-10-06 日本電気株式会社 クロック生成回路

Also Published As

Publication number Publication date
EP0847140A2 (de) 1998-06-10
EP0847140A3 (de) 1998-07-29
JPH10242820A (ja) 1998-09-11
DE69717401T2 (de) 2003-08-14
EP0847140B1 (de) 2002-11-27
US5952863A (en) 1999-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition