US6427162B1
(en)
*
|
1996-05-02 |
2002-07-30 |
Sun Microsystems, Inc. |
Separate code and data contexts: an architectural approach to virtual text sharing
|
US6247040B1
(en)
*
|
1996-09-30 |
2001-06-12 |
Lsi Logic Corporation |
Method and structure for automated switching between multiple contexts in a storage subsystem target device
|
US6081849A
(en)
*
|
1996-10-01 |
2000-06-27 |
Lsi Logic Corporation |
Method and structure for switching multiple contexts in storage subsystem target device
|
JPH11122301A
(ja)
*
|
1997-10-20 |
1999-04-30 |
Fujitsu Ltd |
アドレス変換接続装置
|
US6108760A
(en)
*
|
1997-10-31 |
2000-08-22 |
Silicon Spice |
Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
|
US6122719A
(en)
|
1997-10-31 |
2000-09-19 |
Silicon Spice |
Method and apparatus for retiming in a network of multiple context processing elements
|
US5915123A
(en)
*
|
1997-10-31 |
1999-06-22 |
Silicon Spice |
Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
|
US6633922B1
(en)
*
|
1997-12-15 |
2003-10-14 |
International Business Machines Corporation |
Object access mechanism that dynamically switches between multiple distributed access models
|
US6182210B1
(en)
|
1997-12-16 |
2001-01-30 |
Intel Corporation |
Processor having multiple program counters and trace buffers outside an execution pipeline
|
US6463522B1
(en)
|
1997-12-16 |
2002-10-08 |
Intel Corporation |
Memory system for ordering load and store instructions in a processor that performs multithread execution
|
US6240509B1
(en)
*
|
1997-12-16 |
2001-05-29 |
Intel Corporation |
Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation
|
US6772324B2
(en)
|
1997-12-17 |
2004-08-03 |
Intel Corporation |
Processor having multiple program counters and trace buffers outside an execution pipeline
|
US6226735B1
(en)
*
|
1998-05-08 |
2001-05-01 |
Broadcom |
Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements
|
US6564311B2
(en)
|
1999-01-19 |
2003-05-13 |
Matsushita Electric Industrial Co., Ltd. |
Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit
|
US6745317B1
(en)
|
1999-07-30 |
2004-06-01 |
Broadcom Corporation |
Three level direct communication connections between neighboring multiple context processing elements
|
EP1182571B1
(de)
*
|
2000-08-21 |
2011-01-26 |
Texas Instruments Incorporated |
Auf gemeinsamem Bit basierte TLB-Operationen
|
US6560690B2
(en)
|
2000-12-29 |
2003-05-06 |
Intel Corporation |
System and method for employing a global bit for page sharing in a linear-addressed cache
|
US7073044B2
(en)
*
|
2001-03-30 |
2006-07-04 |
Intel Corporation |
Method and apparatus for sharing TLB entries
|
US6728858B2
(en)
|
2001-03-30 |
2004-04-27 |
Intel Corporation |
Method and apparatus including heuristic for sharing TLB entries
|
US7085889B2
(en)
*
|
2002-03-22 |
2006-08-01 |
Intel Corporation |
Use of a context identifier in a cache memory
|
US7017025B1
(en)
*
|
2002-06-27 |
2006-03-21 |
Mips Technologies, Inc. |
Mechanism for proxy management of multiprocessor virtual memory
|
US7003630B1
(en)
|
2002-06-27 |
2006-02-21 |
Mips Technologies, Inc. |
Mechanism for proxy management of multiprocessor storage hierarchies
|
US7089397B1
(en)
|
2003-07-03 |
2006-08-08 |
Transmeta Corporation |
Method and system for caching attribute data for matching attributes with physical addresses
|
US7093100B2
(en)
*
|
2003-11-14 |
2006-08-15 |
International Business Machines Corporation |
Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes
|
US7206916B2
(en)
*
|
2004-03-08 |
2007-04-17 |
Sun Microsystems, Inc. |
Partial address compares stored in translation lookaside buffer
|
JP4064380B2
(ja)
*
|
2004-07-29 |
2008-03-19 |
富士通株式会社 |
演算処理装置およびその制御方法
|
US20070266199A1
(en)
*
|
2004-09-07 |
2007-11-15 |
Freescale Semiconductor, Inc. |
Virtual Address Cache and Method for Sharing Data Stored in a Virtual Address Cache
|
US8522253B1
(en)
*
|
2005-03-31 |
2013-08-27 |
Guillermo Rozas |
Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
|
EP1736887A3
(de)
|
2005-05-31 |
2009-04-22 |
Stmicroelectronics Sa |
Speicherseitenverzeichnis
|
US8327115B2
(en)
|
2006-04-12 |
2012-12-04 |
Soft Machines, Inc. |
Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
|
CN107368285B
(zh)
|
2006-11-14 |
2020-10-09 |
英特尔公司 |
多线程架构
|
US8799620B2
(en)
|
2007-06-01 |
2014-08-05 |
Intel Corporation |
Linear to physical address translation with support for page attributes
|
WO2008155841A1
(ja)
*
|
2007-06-20 |
2008-12-24 |
Fujitsu Limited |
演算処理装置および演算処理方法
|
US10228949B2
(en)
|
2010-09-17 |
2019-03-12 |
Intel Corporation |
Single cycle multi-branch prediction including shadow cache for early far branch prediction
|
CN103547993B
(zh)
|
2011-03-25 |
2018-06-26 |
英特尔公司 |
通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块
|
CN108108188B
(zh)
|
2011-03-25 |
2022-06-28 |
英特尔公司 |
用于通过使用由可分区引擎实例化的虚拟核来支持代码块执行的存储器片段
|
US9842005B2
(en)
|
2011-03-25 |
2017-12-12 |
Intel Corporation |
Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
|
CN107729267B
(zh)
|
2011-05-20 |
2022-01-25 |
英特尔公司 |
资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
|
TWI548994B
(zh)
|
2011-05-20 |
2016-09-11 |
軟體機器公司 |
以複數個引擎支援指令序列的執行之互連結構
|
KR101703401B1
(ko)
|
2011-11-22 |
2017-02-06 |
소프트 머신즈, 인크. |
다중 엔진 마이크로프로세서용 가속 코드 최적화기
|
WO2013077876A1
(en)
|
2011-11-22 |
2013-05-30 |
Soft Machines, Inc. |
A microprocessor accelerated code optimizer
|
US8930674B2
(en)
|
2012-03-07 |
2015-01-06 |
Soft Machines, Inc. |
Systems and methods for accessing a unified translation lookaside buffer
|
US9430410B2
(en)
|
2012-07-30 |
2016-08-30 |
Soft Machines, Inc. |
Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
|
US9229873B2
(en)
|
2012-07-30 |
2016-01-05 |
Soft Machines, Inc. |
Systems and methods for supporting a plurality of load and store accesses of a cache
|
US9916253B2
(en)
|
2012-07-30 |
2018-03-13 |
Intel Corporation |
Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
|
US9740612B2
(en)
|
2012-07-30 |
2017-08-22 |
Intel Corporation |
Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
|
US9710399B2
(en)
|
2012-07-30 |
2017-07-18 |
Intel Corporation |
Systems and methods for flushing a cache with modified data
|
US9678882B2
(en)
|
2012-10-11 |
2017-06-13 |
Intel Corporation |
Systems and methods for non-blocking implementation of cache flush instructions
|
CN105210040B
(zh)
|
2013-03-15 |
2019-04-02 |
英特尔公司 |
用于执行分组成块的多线程指令的方法
|
US9886279B2
(en)
|
2013-03-15 |
2018-02-06 |
Intel Corporation |
Method for populating and instruction view data structure by using register template snapshots
|
US10275255B2
(en)
|
2013-03-15 |
2019-04-30 |
Intel Corporation |
Method for dependency broadcasting through a source organized source view data structure
|
US9891924B2
(en)
|
2013-03-15 |
2018-02-13 |
Intel Corporation |
Method for implementing a reduced size register view data structure in a microprocessor
|
WO2014150991A1
(en)
|
2013-03-15 |
2014-09-25 |
Soft Machines, Inc. |
A method for implementing a reduced size register view data structure in a microprocessor
|
EP2972836B1
(de)
|
2013-03-15 |
2022-11-09 |
Intel Corporation |
Verfahren zur emulierung einer zentralisierten gast-flag-architektur mithilfe einer nativen verteilten flag-architektur
|
WO2014150971A1
(en)
|
2013-03-15 |
2014-09-25 |
Soft Machines, Inc. |
A method for dependency broadcasting through a block organized source view data structure
|
WO2014150806A1
(en)
|
2013-03-15 |
2014-09-25 |
Soft Machines, Inc. |
A method for populating register view data structure by using register template snapshots
|
US9904625B2
(en)
|
2013-03-15 |
2018-02-27 |
Intel Corporation |
Methods, systems and apparatus for predicting the way of a set associative cache
|
US9811342B2
(en)
|
2013-03-15 |
2017-11-07 |
Intel Corporation |
Method for performing dual dispatch of blocks and half blocks
|
US9569216B2
(en)
|
2013-03-15 |
2017-02-14 |
Soft Machines, Inc. |
Method for populating a source view data structure by using register template snapshots
|
US10140138B2
(en)
|
2013-03-15 |
2018-11-27 |
Intel Corporation |
Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
|
US9317443B2
(en)
|
2014-04-17 |
2016-04-19 |
International Business Machines Corporation |
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
|
US9323692B2
(en)
|
2014-04-17 |
2016-04-26 |
International Business Machines Corporation |
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
|
US10977192B1
(en)
*
|
2016-04-08 |
2021-04-13 |
Amazon Technologies, Inc. |
Real-time memory-page state tracking and its applications
|