DE69630372D1 - Skalierbare vielstufige verbindungsarchitektur - Google Patents

Skalierbare vielstufige verbindungsarchitektur

Info

Publication number
DE69630372D1
DE69630372D1 DE69630372T DE69630372T DE69630372D1 DE 69630372 D1 DE69630372 D1 DE 69630372D1 DE 69630372 T DE69630372 T DE 69630372T DE 69630372 T DE69630372 T DE 69630372T DE 69630372 D1 DE69630372 D1 DE 69630372D1
Authority
DE
Germany
Prior art keywords
routing
innovative
interconnect
tab
connector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69630372T
Other languages
English (en)
Inventor
S Ting
M Pani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BTR Inc
Original Assignee
BTR Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BTR Inc filed Critical BTR Inc
Application granted granted Critical
Publication of DE69630372D1 publication Critical patent/DE69630372D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed

Landscapes

  • Mathematical Physics (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Stereophonic System (AREA)
  • Connector Housings Or Holding Contact Members (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Rectifiers (AREA)
DE69630372T 1995-05-03 1996-04-30 Skalierbare vielstufige verbindungsarchitektur Expired - Lifetime DE69630372D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43304195A 1995-05-03 1995-05-03
PCT/US1996/005964 WO1996035261A1 (en) 1995-05-03 1996-04-30 Scalable multiple level interconnect architecture

Publications (1)

Publication Number Publication Date
DE69630372D1 true DE69630372D1 (de) 2003-11-20

Family

ID=23718622

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69630372T Expired - Lifetime DE69630372D1 (de) 1995-05-03 1996-04-30 Skalierbare vielstufige verbindungsarchitektur

Country Status (10)

Country Link
US (2) US6088526A (de)
EP (2) EP0824791B1 (de)
JP (1) JP3727065B2 (de)
KR (1) KR19990008270A (de)
CN (1) CN1117432C (de)
AT (1) ATE252291T1 (de)
AU (1) AU5718196A (de)
DE (1) DE69630372D1 (de)
TW (1) TW294812B (de)
WO (1) WO1996035261A1 (de)

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US6462578B2 (en) 1993-08-03 2002-10-08 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
US6051991A (en) * 1993-08-03 2000-04-18 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
CN1117432C (zh) 1995-05-03 2003-08-06 Btr公司 可缩放的多层互联结构
US5850564A (en) 1995-05-03 1998-12-15 Btr, Inc, Scalable multiple level tab oriented interconnect architecture
US6034547A (en) 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
US6624658B2 (en) 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US7389487B1 (en) 1998-04-28 2008-06-17 Actel Corporation Dedicated interface architecture for a hybrid integrated circuit
US6407576B1 (en) 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
US6320412B1 (en) 1999-12-20 2001-11-20 Btr, Inc. C/O Corporate Trust Co. Architecture and interconnect for programmable logic circuits
US6636930B1 (en) * 2000-03-06 2003-10-21 Actel Corporation Turn architecture for routing resources in a field programmable gate array
US6861869B1 (en) 2000-03-06 2005-03-01 Actel Corporation Block symmetrization in a field programmable gate array
US7233167B1 (en) 2000-03-06 2007-06-19 Actel Corporation Block symmetrization in a field programmable gate array
US6285212B1 (en) 2000-03-06 2001-09-04 Actel Corporation Block connector splitting in logic block of a field programmable gate array
US6567968B1 (en) * 2000-03-06 2003-05-20 Actel Corporation Block level routing architecture in a field programmable gate array
US6268743B1 (en) 2000-03-06 2001-07-31 Acatel Corporation Block symmetrization in a field programmable gate array
US6476636B1 (en) * 2000-09-02 2002-11-05 Actel Corporation Tileable field-programmable gate array architecture
JP3555080B2 (ja) * 2000-10-19 2004-08-18 Ｎｅｃエレクトロニクス株式会社 汎用ロジックモジュール及びこれを用いたセル
US6605962B2 (en) 2001-05-06 2003-08-12 Altera Corporation PLD architecture for flexible placement of IP function blocks
US6594810B1 (en) 2001-10-04 2003-07-15 M2000 Reconfigurable integrated circuit with a scalable architecture
JP2003338750A (ja) * 2002-05-20 2003-11-28 Nec Electronics Corp 汎用ロジックセル、これを用いた汎用ロジックセルアレイ、及びこの汎用ロジックセルアレイを用いたａｓｉｃ
US7461234B2 (en) * 2002-07-01 2008-12-02 Panasonic Corporation Loosely-biased heterogeneous reconfigurable arrays
US6990010B1 (en) 2003-08-06 2006-01-24 Actel Corporation Deglitching circuits for a radiation-hardened static random access memory based programmable architecture
DE102004063926B4 (de) * 2004-03-24 2017-10-19 Infineon Technologies Ag Konfigurierbare Treiberzelle eines logischen Zellenfeldes
US6975139B2 (en) 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7460529B2 (en) 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
DE102004059673B4 (de) * 2004-12-10 2011-02-03 Infineon Technologies Ag System on Chip, Belichtungsmaskenanordnung und entsprechendes Herstellungsverfahren
US8010826B2 (en) * 2005-09-13 2011-08-30 Meta Systems Reconfigurable circuit with redundant reconfigurable cluster(s)
US7478261B2 (en) * 2005-09-13 2009-01-13 M2000 Reconfigurable circuit with redundant reconfigurable cluster(s)
US7275196B2 (en) 2005-11-23 2007-09-25 M2000 S.A. Runtime reconfiguration of reconfigurable circuits
US7423453B1 (en) 2006-01-20 2008-09-09 Advantage Logic, Inc. Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
WO2008008005A1 (en) * 2006-07-13 2008-01-17 Volvo Lastvagnar Ab Method and system for operating a combustion engine brake
WO2008137511A1 (en) * 2007-05-04 2008-11-13 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits
US7999570B2 (en) 2009-06-24 2011-08-16 Advantage Logic, Inc. Enhanced permutable switching network with multicasting signals for interconnection fabric
US9024037B1 (en) 2011-05-19 2015-05-05 The United States Of America As Represented By The Secretary Of The Air Force Two-photon absorbing polymers based on triarylamine-benzobisthiazole-triarylamine quadrupolar-structure motif
CN103412253B (zh) * 2013-08-05 2016-01-20 电子科技大学 互联结构模型化方法和互联资源配置向量自动生成方法
CN103631754B (zh) * 2013-09-22 2016-07-06 中国科学院电子学研究所 可编程信号处理单元
US10113065B1 (en) 2016-10-31 2018-10-30 The United States Of America, As Represented By The Secretary Of The Air Force Two-photon absorbing compounds and methods of making same
US10336745B2 (en) 2017-03-21 2019-07-02 The United States of America as represented by the Secretery of the Air Force Piperazine-containing two-photon absorbing compounds
CN108427829B (zh) * 2018-02-09 2022-11-08 京微齐力(北京)科技有限公司 一种具有公共线结构的fpga

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US4720780A (en) 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
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US5243208A (en) * 1987-05-27 1993-09-07 Hitachi, Ltd. Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
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US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
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Also Published As

Publication number Publication date
EP1294098A2 (de) 2003-03-19
WO1996035261A1 (en) 1996-11-07
AU5718196A (en) 1996-11-21
EP0824791A1 (de) 1998-02-25
JP3727065B2 (ja) 2005-12-14
CN1117432C (zh) 2003-08-06
US6300793B1 (en) 2001-10-09
CN1188569A (zh) 1998-07-22
JPH11505081A (ja) 1999-05-11
KR19990008270A (ko) 1999-01-25
US6088526A (en) 2000-07-11
EP0824791B1 (de) 2003-10-15
TW294812B (de) 1997-01-01
ATE252291T1 (de) 2003-11-15
EP1294098A3 (de) 2004-11-03

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Legal Events

Date Code Title Description
8332 No legal effect for de