DE69625826T2 - Mechanismus für dynamisch zeitversetzte transaktionen - Google Patents

Mechanismus für dynamisch zeitversetzte transaktionen

Info

Publication number
DE69625826T2
DE69625826T2 DE69625826T DE69625826T DE69625826T2 DE 69625826 T2 DE69625826 T2 DE 69625826T2 DE 69625826 T DE69625826 T DE 69625826T DE 69625826 T DE69625826 T DE 69625826T DE 69625826 T2 DE69625826 T2 DE 69625826T2
Authority
DE
Germany
Prior art keywords
transaction
bus
deferral
processor
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69625826T
Other languages
German (de)
English (en)
Other versions
DE69625826D1 (de
Inventor
Jasmin Ajanovic
M. Dobbins
N. Murdoch
L. Rabe
E. Sailer
Aditya Sreenivas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69625826D1 publication Critical patent/DE69625826D1/de
Publication of DE69625826T2 publication Critical patent/DE69625826T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
DE69625826T 1995-09-05 1996-07-15 Mechanismus für dynamisch zeitversetzte transaktionen Expired - Fee Related DE69625826T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/523,385 US5761444A (en) 1995-09-05 1995-09-05 Method and apparatus for dynamically deferring transactions
PCT/US1996/011716 WO1997011418A2 (en) 1995-09-05 1996-07-15 Dynamic deferred transaction mechanism

Publications (2)

Publication Number Publication Date
DE69625826D1 DE69625826D1 (de) 2003-02-20
DE69625826T2 true DE69625826T2 (de) 2003-11-06

Family

ID=24084778

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69625826T Expired - Fee Related DE69625826T2 (de) 1995-09-05 1996-07-15 Mechanismus für dynamisch zeitversetzte transaktionen

Country Status (9)

Country Link
US (1) US5761444A (enExample)
EP (1) EP0870240B1 (enExample)
KR (1) KR100296633B1 (enExample)
CN (1) CN1146802C (enExample)
AU (1) AU6493796A (enExample)
DE (1) DE69625826T2 (enExample)
MY (1) MY119493A (enExample)
TW (1) TW305031B (enExample)
WO (1) WO1997011418A2 (enExample)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761444A (en) * 1995-09-05 1998-06-02 Intel Corporation Method and apparatus for dynamically deferring transactions
US5928346A (en) * 1996-09-11 1999-07-27 Hewlett-Packard Company Method for enhanced peripheral component interconnect bus split data transfer
DE59606606D1 (de) * 1996-10-08 2001-04-19 Siemens Ag Verfahren und regelungsstruktur zur momentenvorsteuerung numerisch geregelter, elastischer und damit schwingungsfähiger mehrmassensysteme
US5961621A (en) * 1997-03-28 1999-10-05 Intel Corporation Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
US5935233A (en) * 1997-05-21 1999-08-10 Micron Electronics, Inc. Computer system with a switch interconnector for computer devices
US6003112A (en) * 1997-06-30 1999-12-14 Intel Corporation Memory controller and method for clearing or copying memory utilizing register files to store address information
US5889968A (en) * 1997-09-30 1999-03-30 Intel Corporation Method and apparatus for interlocking a broadcast message on a bus
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US6073198A (en) * 1998-03-31 2000-06-06 Micron Electronics, Inc. System for peer-to-peer mastering over a computer bus
US6223238B1 (en) 1998-03-31 2001-04-24 Micron Electronics, Inc. Method of peer-to-peer mastering over a computer bus
US6816934B2 (en) * 2000-12-22 2004-11-09 Hewlett-Packard Development Company, L.P. Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol
US6145039A (en) * 1998-11-03 2000-11-07 Intel Corporation Method and apparatus for an improved interface between computer components
US20030110317A1 (en) * 1998-11-03 2003-06-12 Jasmin Ajanovic Method and apparatus for an improved interface between a memory control hub and an input/output control hub
US6289406B1 (en) * 1998-11-06 2001-09-11 Vlsi Technology, Inc. Optimizing the performance of asynchronous bus bridges with dynamic transactions
US6275887B1 (en) * 1999-03-17 2001-08-14 Intel Corporation Method and apparatus for terminating a bus transaction if the target is not ready
US6374317B1 (en) 1999-10-07 2002-04-16 Intel Corporation Method and apparatus for initializing a computer interface
US6516375B1 (en) 1999-11-03 2003-02-04 Intel Corporation Peripheral component interconnect (PCI) configuration emulation for hub interface
US7039047B1 (en) 1999-11-03 2006-05-02 Intel Corporation Virtual wire signaling
US6694390B1 (en) * 2000-09-11 2004-02-17 Intel Corporation Managing bus transaction dependencies
US6961800B2 (en) * 2001-09-28 2005-11-01 Hewlett-Packard Development Company, L.P. Method for improving processor performance
US7051145B2 (en) * 2001-12-10 2006-05-23 Emulex Design & Manufacturing Corporation Tracking deferred data transfers on a system-interconnect bus
US7080169B2 (en) 2001-12-11 2006-07-18 Emulex Design & Manufacturing Corporation Receiving data from interleaved multiple concurrent transactions in a FIFO memory having programmable buffer zones
US8214531B2 (en) * 2002-10-24 2012-07-03 Emulex Design & Manufacturing Corporation Network configuration synchronization for hardware accelerated network protocol
US7249173B2 (en) 2002-10-25 2007-07-24 Emulex Design & Manufacturing Corporation Abstracted node discovery
CN100337228C (zh) * 2003-12-26 2007-09-12 华为技术有限公司 远程同步调用过程中的超时自适应方法
US7549004B1 (en) * 2004-08-20 2009-06-16 Altera Corporation Split filtering in multilayer systems
US20060129726A1 (en) * 2004-12-09 2006-06-15 International Business Machines Corporation Methods and apparatus for processing a command
US7868390B2 (en) 2007-02-13 2011-01-11 United Microelectronics Corp. Method for fabricating strained-silicon CMOS transistor
US7927954B2 (en) 2007-02-26 2011-04-19 United Microelectronics Corp. Method for fabricating strained-silicon metal-oxide semiconductor transistors
US20080320192A1 (en) * 2007-06-19 2008-12-25 Sundaram Chinthamani Front side bus performance using an early defer-reply mechanism
US9159065B2 (en) 2011-08-15 2015-10-13 Bank Of America Corporation Method and apparatus for object security session validation
US8726339B2 (en) 2011-08-15 2014-05-13 Bank Of America Corporation Method and apparatus for emergency session validation
US8850515B2 (en) 2011-08-15 2014-09-30 Bank Of America Corporation Method and apparatus for subject recognition session validation
US8572686B2 (en) 2011-08-15 2013-10-29 Bank Of America Corporation Method and apparatus for object transaction session validation
US8572688B2 (en) * 2011-08-15 2013-10-29 Bank Of America Corporation Method and apparatus for session validation to access third party resources
US8601541B2 (en) 2011-08-15 2013-12-03 Bank Of America Corporation Method and apparatus for session validation to access mainframe resources
US8572724B2 (en) 2011-08-15 2013-10-29 Bank Of America Corporation Method and apparatus for network session validation
US8572690B2 (en) 2011-08-15 2013-10-29 Bank Of America Corporation Apparatus and method for performing session validation to access confidential resources
US8572687B2 (en) * 2011-08-15 2013-10-29 Bank Of America Corporation Apparatus and method for performing session validation
US8752157B2 (en) 2011-08-15 2014-06-10 Bank Of America Corporation Method and apparatus for third party session validation
US8584201B2 (en) 2011-08-15 2013-11-12 Bank Of America Corporation Method and apparatus for session validation to access from uncontrolled devices
US10481946B2 (en) * 2014-05-12 2019-11-19 Hitachi, Ltd. Information-processing device, processing method thereof, and input/output device
CN106326045B (zh) * 2015-06-30 2019-10-25 展讯通信（上海）有限公司 一种检测总线延时的方法
DE102016212808A1 (de) * 2016-07-13 2018-01-18 Robert Bosch Gmbh Unterbrechungsanforderungs-Verteilereinrichtung und Betriebsverfahren hierfür
US11488141B2 (en) * 2017-09-29 2022-11-01 Apple Inc. Command-based timer for wireless transactions
US11422968B2 (en) * 2020-03-09 2022-08-23 Infineon Technologies LLC Methods, devices and systems for high speed serial bus transactions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3641505A (en) * 1969-06-25 1972-02-08 Bell Telephone Labor Inc Multiprocessor computer adapted for partitioning into a plurality of independently operating systems
US4148012A (en) * 1975-09-26 1979-04-03 Greer Hydraulics, Inc. Access control system
US4991008A (en) * 1988-12-01 1991-02-05 Intec Video Systems, Inc. Automatic transaction surveillance system
US5463753A (en) * 1992-10-02 1995-10-31 Compaq Computer Corp. Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller
US5553248A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal
US5426740A (en) * 1994-01-14 1995-06-20 Ast Research, Inc. Signaling protocol for concurrent bus access in a multiprocessor system
US6182176B1 (en) * 1994-02-24 2001-01-30 Hewlett-Packard Company Queue-based predictive flow control mechanism
US5524216A (en) * 1994-05-13 1996-06-04 Hewlett-Packard Company Coherent transaction ordering in multi-tiered bus system
US5535340A (en) * 1994-05-20 1996-07-09 Intel Corporation Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5761444A (en) * 1995-09-05 1998-06-02 Intel Corporation Method and apparatus for dynamically deferring transactions

Also Published As

Publication number Publication date
AU6493796A (en) 1997-04-09
US5761444A (en) 1998-06-02
EP0870240A4 (en) 2001-10-24
WO1997011418A2 (en) 1997-03-27
DE69625826D1 (de) 2003-02-20
EP0870240A2 (en) 1998-10-14
EP0870240B1 (en) 2003-01-15
WO1997011418A3 (en) 1997-05-09
KR100296633B1 (ko) 2001-08-07
HK1016300A1 (en) 1999-10-29
CN1200823A (zh) 1998-12-02
MY119493A (en) 2005-06-30
TW305031B (enExample) 1997-05-11
KR19990044427A (ko) 1999-06-25
CN1146802C (zh) 2004-04-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee