DE69624493T2 - Vorrichtung und Verfahren zur Unterdrückung von parasitären Effekten in einer integrierten Schaltung mit pn-Isolationszonen - Google Patents

Vorrichtung und Verfahren zur Unterdrückung von parasitären Effekten in einer integrierten Schaltung mit pn-Isolationszonen

Info

Publication number
DE69624493T2
DE69624493T2 DE69624493T DE69624493T DE69624493T2 DE 69624493 T2 DE69624493 T2 DE 69624493T2 DE 69624493 T DE69624493 T DE 69624493T DE 69624493 T DE69624493 T DE 69624493T DE 69624493 T2 DE69624493 T2 DE 69624493T2
Authority
DE
Germany
Prior art keywords
integrated circuit
parasitic effects
isolation zones
suppressing parasitic
suppressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69624493T
Other languages
English (en)
Other versions
DE69624493D1 (de
Inventor
Enrico Maria Ravanelli
Massimo Pozzoni
Giorgio Pedrazzini
Giulio Ricotti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69624493D1 publication Critical patent/DE69624493D1/de
Application granted granted Critical
Publication of DE69624493T2 publication Critical patent/DE69624493T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69624493T 1996-12-09 1996-12-09 Vorrichtung und Verfahren zur Unterdrückung von parasitären Effekten in einer integrierten Schaltung mit pn-Isolationszonen Expired - Fee Related DE69624493T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830614A EP0847089B1 (de) 1996-12-09 1996-12-09 Vorrichtung und Verfahren zur Unterdrückung von parasitären Effekten in einer integrierten Schaltung mit pn-Isolationszonen

Publications (2)

Publication Number Publication Date
DE69624493D1 DE69624493D1 (de) 2002-11-28
DE69624493T2 true DE69624493T2 (de) 2003-06-26

Family

ID=8226072

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69624493T Expired - Fee Related DE69624493T2 (de) 1996-12-09 1996-12-09 Vorrichtung und Verfahren zur Unterdrückung von parasitären Effekten in einer integrierten Schaltung mit pn-Isolationszonen

Country Status (4)

Country Link
US (2) US6060758A (de)
EP (1) EP0847089B1 (de)
JP (1) JPH10173128A (de)
DE (1) DE69624493T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10350162A1 (de) * 2003-10-28 2005-06-09 Infineon Technologies Ag Halbleiterbauteil

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1305634B1 (it) * 1998-01-19 2001-05-15 Sgs Thomson Microelectronics Protezione da effetti di sottomassa o di sovralimentazione percircuiti integrati ad isolamento a giunzione
DE69902877D1 (de) * 1999-04-30 2002-10-17 St Microelectronics Srl Integrierter Schaltkreis mit einer Leistungsschaltung und einer Steuerschaltung, ohne parasitäre Ströme
DE19928762C1 (de) * 1999-06-23 2000-11-23 Siemens Ag Schaltungsanordnung zur Verhinderung der Injektion von Minoritätsladungsträgern in das Substrat
EP1130648A1 (de) 2000-02-29 2001-09-05 STMicroelectronics S.r.l. Verfahren und Bauelement zur Begrenzung des Substratpotentials in pn-übergangsisolierten integrierten Schaltkreisen
US6737713B2 (en) * 2001-07-03 2004-05-18 Tripath Technology, Inc. Substrate connection in an integrated power circuit
GB0308345D0 (en) * 2003-04-11 2003-05-14 Power Electronics Design Ct Power intregrated circuits
US7446378B2 (en) * 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
US7184253B1 (en) * 2006-01-13 2007-02-27 Cypress Semiconductor Corporation ESD trigger circuit with injected current compensation
US7855862B1 (en) 2006-03-28 2010-12-21 Cypress Semiconductor Corporation Electrostatic discharge (ESD) circuit and method that includes P-channel device in signal path
EP1965425A1 (de) * 2007-03-01 2008-09-03 Infineon Technologies Austria AG Integrierte Schaltungsanordnung mit Gegenspannungsschutz
US8013475B2 (en) 2007-03-15 2011-09-06 Infineon Technologies Ag Reverse voltage protected integrated circuit arrangement for multiple supply lines
IT201800000947A1 (it) * 2018-01-15 2019-07-15 St Microelectronics Srl Piastrina a semiconduttore con condensatore sepolto, e metodo di fabbricazione della piastrina a semiconduttore
FR3083919A1 (fr) * 2018-07-13 2020-01-17 Stmicroelectronics (Rousset) Sas Puce electronique protegee
DE102020107479A1 (de) * 2020-03-18 2021-09-23 Elmos Semiconductor Se Vorrichtung und Verfahren zur Verhinderung der Nichtzündung unbeschädigter Airbag-Zündkreise bei einem Unfall

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4211941A (en) * 1978-08-03 1980-07-08 Rca Corporation Integrated circuitry including low-leakage capacitance
US4496849A (en) * 1982-02-22 1985-01-29 General Motors Corporation Power transistor protection from substrate injection
IT1213260B (it) * 1984-12-18 1989-12-14 Sgs Thomson Microelectronics Circuito a ponte di transistori mos di potenza a canale n integrato eprocedimento per la sua fabbricazione.
US5132235A (en) * 1987-08-07 1992-07-21 Siliconix Incorporated Method for fabricating a high voltage MOS transistor
US5051612A (en) * 1989-02-10 1991-09-24 Texas Instruments Incorporated Prevention of parasitic mechanisms in junction isolated devices
US5040035A (en) * 1989-12-22 1991-08-13 At&T Bell Laboratories MOS devices having improved threshold match
DE69128936T2 (de) * 1991-11-25 1998-07-16 St Microelectronics Srl Hochstrom-MOS-Transistor enthaltende integrierte Brückenstruktur mit optimierten Übertragungsleistungsverlusten
IT1252623B (it) * 1991-12-05 1995-06-19 Sgs Thomson Microelectronics Dispositivo a semiconduttore comprendente almeno un transistor di potenza e almeno un circuito di comando, con circuito di isolamento dinamico,integrati in maniera monolitica nella stessa piastrina
WO1993018550A1 (en) * 1992-03-10 1993-09-16 Analog Devices, Inc. A circuit construction for protective biasing
JPH06303137A (ja) * 1992-12-29 1994-10-28 Hitachi Ltd Ｄ／ａ変換器、オフセット調整回路及びこれを用いた携帯通信端末装置
EP0703620B1 (de) * 1994-09-21 2001-01-10 STMicroelectronics S.r.l. Schaltung zur Verhinderung der Zündung von parasitären Bauelementen in integrierten Schaltungen bestehend aus einer Leistungsstufe und einer Niederspannungssteuerschaltung
US5687067A (en) * 1995-05-30 1997-11-11 Philips Electronics North America Corporation Low noise controller for pulse width modulated converters
US5610079A (en) * 1995-06-19 1997-03-11 Reliance Electric Industrial Company Self-biased moat for parasitic current suppression in integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10350162A1 (de) * 2003-10-28 2005-06-09 Infineon Technologies Ag Halbleiterbauteil
DE10350162B4 (de) * 2003-10-28 2011-07-28 Infineon Technologies AG, 81669 Halbleiterbauteil

Also Published As

Publication number Publication date
JPH10173128A (ja) 1998-06-26
US6060758A (en) 2000-05-09
US6248616B1 (en) 2001-06-19
DE69624493D1 (de) 2002-11-28
EP0847089B1 (de) 2002-10-23
EP0847089A1 (de) 1998-06-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee