DE69620510D1 - Integrierte schaltungen mit randlosen kontaktlöchern - Google Patents

Integrierte schaltungen mit randlosen kontaktlöchern

Info

Publication number
DE69620510D1
DE69620510D1 DE69620510T DE69620510T DE69620510D1 DE 69620510 D1 DE69620510 D1 DE 69620510D1 DE 69620510 T DE69620510 T DE 69620510T DE 69620510 T DE69620510 T DE 69620510T DE 69620510 D1 DE69620510 D1 DE 69620510D1
Authority
DE
Germany
Prior art keywords
frontless
integrated circuits
contact holes
holes
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69620510T
Other languages
English (en)
Other versions
DE69620510T2 (de
Inventor
Henry Wei-Ming Chung
Kevin Carl Brown
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of DE69620510D1 publication Critical patent/DE69620510D1/de
Application granted granted Critical
Publication of DE69620510T2 publication Critical patent/DE69620510T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69620510T 1995-02-03 1996-01-30 Integrierte schaltungen mit randlosen kontaktlöchern Expired - Lifetime DE69620510T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38359795A 1995-02-03 1995-02-03
PCT/US1996/001340 WO1996024164A1 (en) 1995-02-03 1996-01-30 Integrated circuits with borderless vias

Publications (2)

Publication Number Publication Date
DE69620510D1 true DE69620510D1 (de) 2002-05-16
DE69620510T2 DE69620510T2 (de) 2002-11-07

Family

ID=23513849

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620510T Expired - Lifetime DE69620510T2 (de) 1995-02-03 1996-01-30 Integrierte schaltungen mit randlosen kontaktlöchern

Country Status (4)

Country Link
US (1) US5757077A (de)
EP (1) EP0754351B1 (de)
DE (1) DE69620510T2 (de)
WO (1) WO1996024164A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652173A (en) * 1996-05-09 1997-07-29 Philips Electronics North America Corporation Monolithic microwave circuit with thick conductors
US6016012A (en) * 1996-11-05 2000-01-18 Cypress Semiconductor Corporation Thin liner layer providing reduced via resistance
KR19980064250A (ko) * 1996-12-18 1998-10-07 윌리엄비.켐플러 다중 레벨 금속화를 위한 완전히 인캡슐레이팅된 금속 리드
JP3098450B2 (ja) * 1997-04-21 2000-10-16 日本電気アイシーマイコンシステム株式会社 半導体集積回路
US6194313B1 (en) * 1997-04-30 2001-02-27 Texas Instruments Incorporated Method for reducing recess for the formation of local interconnect and or plug trench fill for etchback process
US5925932A (en) * 1997-12-18 1999-07-20 Advanced Micro Devices, Inc. Borderless vias
US5982035A (en) 1998-06-15 1999-11-09 Advanced Micro Devices, Inc. High integrity borderless vias with protective sidewall spacer
US6239026B1 (en) 1998-09-28 2001-05-29 Conexant Systems, Inc. Nitride etch stop for poisoned unlanded vias
US6165695A (en) * 1998-12-01 2000-12-26 Advanced Micro Devices, Inc. Thin resist with amorphous silicon hard mask for via etch application
US6127070A (en) * 1998-12-01 2000-10-03 Advanced Micro Devices, Inc. Thin resist with nitride hard mask for via etch application
US6162587A (en) * 1998-12-01 2000-12-19 Advanced Micro Devices Thin resist with transition metal hard mask for via etch application
US6046103A (en) * 1999-08-02 2000-04-04 Taiwan Semiconductor Manufacturing Company Borderless contact process for a salicide devices
US6339027B1 (en) * 1999-11-22 2002-01-15 Chartered Semiconductor Manufacturing Ltd. Process for borderless stop in tin via formation
KR100382730B1 (ko) * 2000-12-14 2003-05-09 삼성전자주식회사 반도체 소자의 금속 컨택 구조체 및 그 형성방법
US20030001188A1 (en) * 2001-06-27 2003-01-02 Nakagawa Osamu Samuel High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems
US7188321B2 (en) * 2003-11-06 2007-03-06 International Business Machines Corporation Generation of metal holes by via mutation
KR100876957B1 (ko) * 2006-10-20 2009-01-07 삼성전자주식회사 노어형 불 휘발성 메모리 소자 및 이를 형성하기 위한 형성방법
US9685368B2 (en) 2015-06-26 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure having an etch stop layer over conductive lines

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
US4656732A (en) * 1984-09-26 1987-04-14 Texas Instruments Incorporated Integrated circuit fabrication process
JPS63224240A (ja) * 1987-03-12 1988-09-19 Fuji Xerox Co Ltd 半導体集積回路装置
US4948755A (en) * 1987-10-08 1990-08-14 Standard Microsystems Corporation Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition
FR2658951B1 (fr) * 1990-02-23 1992-05-07 Bonis Maurice Procede de fabrication d'un circuit integre pour filiere analogique rapide utilisant des lignes d'interconnexions locales en siliciure.
JPH04226054A (ja) * 1990-03-02 1992-08-14 Toshiba Corp 多層配線構造を有する半導体装置及びその製造方法
US5243220A (en) * 1990-03-23 1993-09-07 Kabushiki Kaisha Toshiba Semiconductor device having miniaturized contact electrode and wiring structure
DE69121535T2 (de) * 1990-12-07 1997-01-02 At & T Corp Feldeffekttransistor mit inverser T-förmiger Silizid-Torelektrode
US5124280A (en) * 1991-01-31 1992-06-23 Sgs-Thomson Microelectronics, Inc. Local interconnect for integrated circuits
JP2990870B2 (ja) * 1991-07-18 1999-12-13 松下電器産業株式会社 半導体集積回路装置及びその製造方法
US5291066A (en) * 1991-11-14 1994-03-01 General Electric Company Moisture-proof electrical circuit high density interconnect module and method for making same
US5262353A (en) * 1992-02-03 1993-11-16 Motorola, Inc. Process for forming a structure which electrically shields conductors
US5286674A (en) * 1992-03-02 1994-02-15 Motorola, Inc. Method for forming a via structure and semiconductor device having the same
US5321211A (en) * 1992-04-30 1994-06-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit via structure
US5317192A (en) * 1992-05-06 1994-05-31 Sgs-Thomson Microelectronics, Inc. Semiconductor contact via structure having amorphous silicon side walls
JP2861629B2 (ja) * 1992-05-27 1999-02-24 日本電気株式会社 半導体装置
TW219407B (de) * 1992-06-24 1994-01-21 American Telephone & Telegraph
US5466636A (en) * 1992-09-17 1995-11-14 International Business Machines Corporation Method of forming borderless contacts using a removable mandrel
JPH06104341A (ja) * 1992-09-18 1994-04-15 Toshiba Corp 半導体集積回路およびその製造方法
JP2830658B2 (ja) * 1992-11-25 1998-12-02 日本電気株式会社 微細金属配線形成方法
US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches

Also Published As

Publication number Publication date
EP0754351A1 (de) 1997-01-22
WO1996024164A1 (en) 1996-08-08
DE69620510T2 (de) 2002-11-07
EP0754351B1 (de) 2002-04-10
US5757077A (en) 1998-05-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition