DE69620199D1 - Verfahren zur Herstellung nichtflüchtiger Speicherzellen mit floating Gates - Google Patents

Verfahren zur Herstellung nichtflüchtiger Speicherzellen mit floating Gates

Info

Publication number
DE69620199D1
DE69620199D1 DE69620199T DE69620199T DE69620199D1 DE 69620199 D1 DE69620199 D1 DE 69620199D1 DE 69620199 T DE69620199 T DE 69620199T DE 69620199 T DE69620199 T DE 69620199T DE 69620199 D1 DE69620199 D1 DE 69620199D1
Authority
DE
Germany
Prior art keywords
production
volatile memory
memory cells
floating gates
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69620199T
Other languages
English (en)
Inventor
Emilio Ghio
Simone Alba
Andrea Colognese
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69620199D1 publication Critical patent/DE69620199D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69620199T 1996-12-16 1996-12-16 Verfahren zur Herstellung nichtflüchtiger Speicherzellen mit floating Gates Expired - Lifetime DE69620199D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830624A EP0848422B1 (de) 1996-12-16 1996-12-16 Verfahren zur Herstellung nichtflüchtiger Speicherzellen mit floating Gates

Publications (1)

Publication Number Publication Date
DE69620199D1 true DE69620199D1 (de) 2002-05-02

Family

ID=8226076

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69620199T Expired - Lifetime DE69620199D1 (de) 1996-12-16 1996-12-16 Verfahren zur Herstellung nichtflüchtiger Speicherzellen mit floating Gates

Country Status (3)

Country Link
US (1) US5888836A (de)
EP (1) EP0848422B1 (de)
DE (1) DE69620199D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350673B1 (en) * 1998-08-13 2002-02-26 Texas Instruments Incorporated Method for decreasing CHC degradation
US6350651B1 (en) * 1999-06-10 2002-02-26 Intel Corporation Method for making flash memory with UV opaque passivation layer
US6605484B2 (en) * 2001-11-30 2003-08-12 Axcelis Technologies, Inc. Process for optically erasing charge buildup during fabrication of an integrated circuit
CN1317747C (zh) * 2003-11-04 2007-05-23 统宝光电股份有限公司 半导体装置钝化方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59184569A (ja) * 1983-04-05 1984-10-19 Oki Electric Ind Co Ltd 不揮発性記憶装置の製造方法
JPS63182826A (ja) * 1987-01-26 1988-07-28 Hitachi Ltd 半導体製造装置
JPS63316439A (ja) * 1987-06-19 1988-12-23 Fuji Electric Co Ltd プラズマ反応利用処理方法
US4916082A (en) * 1989-03-14 1990-04-10 Motorola Inc. Method of preventing dielectric degradation or rupture
EP0408054A3 (en) * 1989-07-14 1991-10-30 Kabushiki Kaisha Toshiba Ultraviolet erasable non-volatile semiconductor memory apparatus
JP3016607B2 (ja) * 1991-02-01 2000-03-06 沖電気工業株式会社 不揮発性メモリの製造方法
JP2666596B2 (ja) * 1991-04-15 1997-10-22 株式会社デンソー 酸化膜中のトラップ密度低減方法、及び半導体装置の製造方法
US5254497A (en) * 1992-07-06 1993-10-19 Taiwan Semiconductor Manufacturing Company Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit
US5587330A (en) * 1994-10-20 1996-12-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US5656521A (en) * 1995-01-12 1997-08-12 Advanced Micro Devices, Inc. Method of erasing UPROM transistors

Also Published As

Publication number Publication date
US5888836A (en) 1999-03-30
EP0848422B1 (de) 2002-03-27
EP0848422A1 (de) 1998-06-17

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Legal Events

Date Code Title Description
8332 No legal effect for de