DE69614917D1 - Kompiler und Prozessor zur schnellen Verarbeitung von Schleifen - Google Patents

Kompiler und Prozessor zur schnellen Verarbeitung von Schleifen

Info

Publication number
DE69614917D1
DE69614917D1 DE69614917T DE69614917T DE69614917D1 DE 69614917 D1 DE69614917 D1 DE 69614917D1 DE 69614917 T DE69614917 T DE 69614917T DE 69614917 T DE69614917 T DE 69614917T DE 69614917 D1 DE69614917 D1 DE 69614917D1
Authority
DE
Germany
Prior art keywords
compiler
loops
processor
fast processing
fast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69614917T
Other languages
English (en)
Other versions
DE69614917T2 (de
Inventor
Shuichi Takayama
Nobuo Higaki
Nobuki Tominaga
Shinya Miyaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69614917D1 publication Critical patent/DE69614917D1/de
Application granted granted Critical
Publication of DE69614917T2 publication Critical patent/DE69614917T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/447—Target code generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
DE69614917T 1995-05-12 1996-02-23 Kompiler und Prozessor zur schnellen Verarbeitung von Schleifen Expired - Lifetime DE69614917T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7114520A JP2987311B2 (ja) 1995-05-12 1995-05-12 プロセッサ及び翻訳装置

Publications (2)

Publication Number Publication Date
DE69614917D1 true DE69614917D1 (de) 2001-10-11
DE69614917T2 DE69614917T2 (de) 2002-01-17

Family

ID=14639814

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69614917T Expired - Lifetime DE69614917T2 (de) 1995-05-12 1996-02-23 Kompiler und Prozessor zur schnellen Verarbeitung von Schleifen

Country Status (7)

Country Link
US (1) US5850551A (de)
EP (1) EP0742518B1 (de)
JP (1) JP2987311B2 (de)
KR (1) KR100253655B1 (de)
CN (1) CN1143213C (de)
DE (1) DE69614917T2 (de)
TW (1) TW294802B (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214203A (ja) * 1997-01-29 1998-08-11 Nec Corp 情報処理装置
US6189092B1 (en) * 1997-06-30 2001-02-13 Matsushita Electric Industrial Co., Ltd. Pipeline processor capable of reducing branch hazards with small-scale circuit
US6085315A (en) * 1997-09-12 2000-07-04 Siemens Aktiengesellschaft Data processing device with loop pipeline
US6076159A (en) * 1997-09-12 2000-06-13 Siemens Aktiengesellschaft Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline
US6233676B1 (en) * 1999-03-18 2001-05-15 Ip-First, L.L.C. Apparatus and method for fast forward branch
US20020087851A1 (en) * 2000-12-28 2002-07-04 Matsushita Electric Industrial Co., Ltd. Microprocessor and an instruction converter
US7278137B1 (en) 2001-12-26 2007-10-02 Arc International Methods and apparatus for compiling instructions for a data processor
JP3886870B2 (ja) * 2002-09-06 2007-02-28 株式会社ルネサステクノロジ データ処理装置
US7457936B2 (en) * 2003-11-19 2008-11-25 Intel Corporation Memory access instruction vectorization
JP5043560B2 (ja) 2007-08-24 2012-10-10 パナソニック株式会社 プログラム実行制御装置
JP5692089B2 (ja) * 2009-11-24 2015-04-01 日本電気株式会社 プロセッサ、プロセッサによるループ回数制御方法
US9043769B2 (en) * 2009-12-28 2015-05-26 Hyperion Core Inc. Optimization of loops and data flow sections in multi-core processor environment
US10241793B2 (en) * 2013-03-15 2019-03-26 Analog Devices Global Paralleizing loops in the presence of possible memory aliases

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4463422A (en) * 1982-07-12 1984-07-31 Csp, Inc. Method of processing an iterative program loop
JPS6051948A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 情報処理装置
JP2708405B2 (ja) * 1986-03-03 1998-02-04 株式会社日立製作所 コンパイラにおけるループ展開方法
US4933837A (en) * 1986-12-01 1990-06-12 Advanced Micro Devices, Inc. Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories
JP3102027B2 (ja) * 1990-11-20 2000-10-23 日本電気株式会社 ループ制御のネスティング管理機構
US5450585A (en) * 1991-05-15 1995-09-12 International Business Machines Corporation Compiler with delayed conditional branching
GB2285154B (en) * 1993-12-24 1998-04-01 Advanced Risc Mach Ltd Branch cache

Also Published As

Publication number Publication date
JPH08314719A (ja) 1996-11-29
EP0742518A2 (de) 1996-11-13
EP0742518A3 (de) 1997-05-28
KR100253655B1 (ko) 2000-04-15
KR960042425A (ko) 1996-12-21
DE69614917T2 (de) 2002-01-17
CN1138175A (zh) 1996-12-18
TW294802B (de) 1997-01-01
JP2987311B2 (ja) 1999-12-06
EP0742518B1 (de) 2001-09-05
US5850551A (en) 1998-12-15
CN1143213C (zh) 2004-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP