DE69522163D1 - Schnittstellenschaltung - Google Patents
SchnittstellenschaltungInfo
- Publication number
- DE69522163D1 DE69522163D1 DE69522163T DE69522163T DE69522163D1 DE 69522163 D1 DE69522163 D1 DE 69522163D1 DE 69522163 T DE69522163 T DE 69522163T DE 69522163 T DE69522163 T DE 69522163T DE 69522163 D1 DE69522163 D1 DE 69522163D1
- Authority
- DE
- Germany
- Prior art keywords
- interface circuit
- interface
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26112094A JP3353260B2 (ja) | 1994-09-30 | 1994-09-30 | インターフェイス回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69522163D1 true DE69522163D1 (de) | 2001-09-20 |
DE69522163T2 DE69522163T2 (de) | 2001-11-22 |
Family
ID=17357381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69522163T Expired - Fee Related DE69522163T2 (de) | 1994-09-30 | 1995-09-28 | Schnittstellenschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5661482A (de) |
EP (1) | EP0707276B1 (de) |
JP (1) | JP3353260B2 (de) |
DE (1) | DE69522163T2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6281831B1 (en) * | 1997-05-15 | 2001-08-28 | Yozan Inc. | Analog to digital converter |
US6075476A (en) * | 1998-11-12 | 2000-06-13 | Intel Corporation | Method and circuit for data dependent voltage bias level |
US6816100B1 (en) | 1999-03-12 | 2004-11-09 | The Regents Of The University Of California | Analog-to-digital converters with common-mode rejection dynamic element matching, including as used in delta-sigma modulators |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4209852A (en) * | 1974-11-11 | 1980-06-24 | Hyatt Gilbert P | Signal processing and memory arrangement |
FR2469836A1 (fr) * | 1979-11-16 | 1981-05-22 | Hennion Bernard | Systeme de codage et decodage a multiniveaux en courant |
US4654815A (en) * | 1985-02-07 | 1987-03-31 | Texas Instruments Incorporated | Analog signal conditioning and digitizing integrated circuit |
US4604983A (en) * | 1985-04-09 | 1986-08-12 | Carp Ralph W | Analog duty cycle to BCD converter |
US4894657A (en) * | 1988-11-25 | 1990-01-16 | General Electric Company | Pipelined analog-to-digital architecture with parallel-autozero analog signal processing |
JPH04301740A (ja) * | 1991-03-29 | 1992-10-26 | Shimadzu Corp | 調芯機構付き材料試験機 |
JP3042568B2 (ja) * | 1992-10-13 | 2000-05-15 | 株式会社鷹山 | インターフェイス回路 |
US5450023A (en) * | 1994-04-18 | 1995-09-12 | Yozan Inc. | Interface circuit using a limited number of pins in LSI applications |
-
1994
- 1994-09-30 JP JP26112094A patent/JP3353260B2/ja not_active Expired - Fee Related
-
1995
- 1995-09-28 DE DE69522163T patent/DE69522163T2/de not_active Expired - Fee Related
- 1995-09-28 EP EP95115334A patent/EP0707276B1/de not_active Expired - Lifetime
- 1995-09-29 US US08/536,243 patent/US5661482A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3353260B2 (ja) | 2002-12-03 |
US5661482A (en) | 1997-08-26 |
EP0707276A1 (de) | 1996-04-17 |
JPH08102674A (ja) | 1996-04-16 |
DE69522163T2 (de) | 2001-11-22 |
EP0707276B1 (de) | 2001-08-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: YOZAN, INC., TOKIO/TOKYO, JP Owner name: SHARP K.K., OSAKA, JP |
|
8339 | Ceased/non-payment of the annual fee |