DE69518506D1 - Verfahren zur strukturierung von leiterbahnen ohne unterätzung - Google Patents

Verfahren zur strukturierung von leiterbahnen ohne unterätzung

Info

Publication number
DE69518506D1
DE69518506D1 DE69518506T DE69518506T DE69518506D1 DE 69518506 D1 DE69518506 D1 DE 69518506D1 DE 69518506 T DE69518506 T DE 69518506T DE 69518506 T DE69518506 T DE 69518506T DE 69518506 D1 DE69518506 D1 DE 69518506D1
Authority
DE
Germany
Prior art keywords
structuring
paths
understanding
structuring paths
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69518506T
Other languages
English (en)
Other versions
DE69518506T2 (de
Inventor
Lewis Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69518506D1 publication Critical patent/DE69518506D1/de
Application granted granted Critical
Publication of DE69518506T2 publication Critical patent/DE69518506T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE69518506T 1995-01-03 1995-11-03 Verfahren zur strukturierung von leiterbahnen ohne unterätzung Expired - Lifetime DE69518506T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/368,170 US5702564A (en) 1995-01-03 1995-01-03 Method of etching conductive lines without undercutting
PCT/US1995/014222 WO1996021243A1 (en) 1995-01-03 1995-11-03 Method of etching conductive lines without undercutting

Publications (2)

Publication Number Publication Date
DE69518506D1 true DE69518506D1 (de) 2000-09-28
DE69518506T2 DE69518506T2 (de) 2001-04-19

Family

ID=23450128

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69518506T Expired - Lifetime DE69518506T2 (de) 1995-01-03 1995-11-03 Verfahren zur strukturierung von leiterbahnen ohne unterätzung

Country Status (7)

Country Link
US (1) US5702564A (de)
EP (1) EP0748518B1 (de)
JP (1) JP3682067B2 (de)
KR (1) KR100376937B1 (de)
DE (1) DE69518506T2 (de)
TW (1) TW273630B (de)
WO (1) WO1996021243A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2924723B2 (ja) * 1995-08-16 1999-07-26 日本電気株式会社 ドライエッチング方法
US5976986A (en) * 1996-08-06 1999-11-02 International Business Machines Corp. Low pressure and low power C12 /HC1 process for sub-micron metal etching
US5901964A (en) * 1997-02-06 1999-05-11 John R. Williams Seal for a longitudinally movable drillstring component
US5918126A (en) * 1997-02-25 1999-06-29 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size
US5918129A (en) * 1997-02-25 1999-06-29 Advanced Micro Devices, Inc. Method of channel doping using diffusion from implanted polysilicon
US6221792B1 (en) * 1997-06-24 2001-04-24 Lam Research Corporation Metal and metal silicide nitridization in a high density, low pressure plasma reactor
JP3957856B2 (ja) * 1998-02-19 2007-08-15 富士通株式会社 半導体装置の製造方法
US6159794A (en) * 1998-05-12 2000-12-12 Advanced Micro Devices, Inc. Methods for removing silicide residue in a semiconductor device
US6057603A (en) * 1998-07-30 2000-05-02 Advanced Micro Devices, Inc. Fabrication of integrated circuit inter-level dielectrics using a stop-on-metal dielectric polish process
TW428256B (en) * 1999-01-25 2001-04-01 United Microelectronics Corp Structure of conducting-wire layer and its fabricating method
US6919272B2 (en) * 2003-02-01 2005-07-19 Newport Fab, Llc Method for patterning densely packed metal segments in a semiconductor die and related structure
KR100604535B1 (ko) 2004-12-31 2006-07-24 동부일렉트로닉스 주식회사 금속 피팅 개선 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4457820A (en) * 1981-12-24 1984-07-03 International Business Machines Corporation Two step plasma etching
JPH01220446A (ja) * 1988-02-29 1989-09-04 Oki Electric Ind Co Ltd ドライエッチング方法
JP3170791B2 (ja) * 1990-09-11 2001-05-28 ソニー株式会社 Ａｌ系材料膜のエッチング方法
JPH04125924A (ja) * 1990-09-17 1992-04-27 Mitsubishi Electric Corp プラズマエッチング方法
US5211804A (en) * 1990-10-16 1993-05-18 Oki Electric Industry, Co., Ltd. Method for dry etching
US5167762A (en) * 1991-01-02 1992-12-01 Micron Technology, Inc. Anisotropic etch method
JPH05267249A (ja) * 1992-03-18 1993-10-15 Hitachi Ltd ドライエッチング方法及びドライエッチング装置
JPH06151382A (ja) * 1992-11-11 1994-05-31 Toshiba Corp ドライエッチング方法
US5350488A (en) * 1992-12-10 1994-09-27 Applied Materials, Inc. Process for etching high copper content aluminum films
US5387556A (en) * 1993-02-24 1995-02-07 Applied Materials, Inc. Etching aluminum and its alloys using HC1, C1-containing etchant and N.sub.2
JPH0794469A (ja) * 1993-09-24 1995-04-07 Sony Corp ドライエッチング方法

Also Published As

Publication number Publication date
EP0748518A1 (de) 1996-12-18
KR100376937B1 (ko) 2003-06-11
TW273630B (en) 1996-04-01
WO1996021243A1 (en) 1996-07-11
JP3682067B2 (ja) 2005-08-10
US5702564A (en) 1997-12-30
DE69518506T2 (de) 2001-04-19
EP0748518B1 (de) 2000-08-23
JPH09510324A (ja) 1997-10-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY