DE69515820T2 - Hochgeschwindigkeitsparallel-/Serienschnittstelle - Google Patents

Hochgeschwindigkeitsparallel-/Serienschnittstelle

Info

Publication number
DE69515820T2
DE69515820T2 DE69515820T DE69515820T DE69515820T2 DE 69515820 T2 DE69515820 T2 DE 69515820T2 DE 69515820 T DE69515820 T DE 69515820T DE 69515820 T DE69515820 T DE 69515820T DE 69515820 T2 DE69515820 T2 DE 69515820T2
Authority
DE
Germany
Prior art keywords
high speed
serial interface
speed parallel
parallel
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69515820T
Other languages
English (en)
Other versions
DE69515820D1 (de
Inventor
Farhad Rostamian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Application granted granted Critical
Publication of DE69515820D1 publication Critical patent/DE69515820D1/de
Publication of DE69515820T2 publication Critical patent/DE69515820T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
DE69515820T 1994-12-13 1995-12-13 Hochgeschwindigkeitsparallel-/Serienschnittstelle Expired - Fee Related DE69515820T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/355,374 US5572721A (en) 1994-12-13 1994-12-13 High speed serial interface between image enhancement logic and ros for implementation of image enhancement algorithms

Publications (2)

Publication Number Publication Date
DE69515820D1 DE69515820D1 (de) 2000-04-27
DE69515820T2 true DE69515820T2 (de) 2000-07-27

Family

ID=23397216

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69515820T Expired - Fee Related DE69515820T2 (de) 1994-12-13 1995-12-13 Hochgeschwindigkeitsparallel-/Serienschnittstelle

Country Status (5)

Country Link
US (1) US5572721A (de)
EP (1) EP0717496B1 (de)
JP (1) JPH08237142A (de)
BR (1) BR9505748A (de)
DE (1) DE69515820T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768529A (en) * 1995-05-05 1998-06-16 Silicon Graphics, Inc. System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers
US5790166A (en) * 1997-07-17 1998-08-04 Xerox Corporation Modulator for doubling resolution in the fast-scan direction for a laser imager in an electrophotographic printer
US6665360B1 (en) * 1999-12-20 2003-12-16 Cypress Semiconductor Corp. Data transmitter with sequential serialization
JP4412788B2 (ja) * 2000-01-24 2010-02-10 株式会社ルネサステクノロジ パラレル−シリアル変換回路
JP2003317401A (ja) * 2002-04-25 2003-11-07 Sanyo Electric Co Ltd データ記録制御装置
KR100611981B1 (ko) * 2004-05-01 2006-08-11 삼성전자주식회사 이미지의 하프토닝 방법 및 장치
US7161846B2 (en) * 2004-11-16 2007-01-09 Seiko Epson Corporation Dual-edge triggered multiplexer flip-flop and method
US7079055B2 (en) * 2004-11-16 2006-07-18 Seiko Epson Corporation Low-power serializer with half-rate clocking and method
US7489754B2 (en) * 2005-02-08 2009-02-10 Agere Systems Inc. Frequency-lock detector
JP2007096903A (ja) * 2005-09-29 2007-04-12 Rohm Co Ltd パラレルシリアル変換回路およびそれを用いた電子機器
US20080063129A1 (en) * 2006-09-11 2008-03-13 Nokia Corporation System and method for pre-defined wake-up of high speed serial link
JP5471509B2 (ja) * 2010-01-26 2014-04-16 富士通株式会社 パラレル−シリアル変換器
JP2011160369A (ja) 2010-02-04 2011-08-18 Sony Corp 電子回路、電子機器、デジタル信号処理方法
US8405426B2 (en) 2010-05-28 2013-03-26 Qualcomm Incorporated Method and apparatus to serialize parallel data input values
US8832487B2 (en) 2011-06-28 2014-09-09 Microsoft Corporation High-speed I/O data system
US8415980B2 (en) 2011-06-28 2013-04-09 Microsoft Corporation Serializing transmitter
JP6060637B2 (ja) 2012-11-14 2017-01-18 株式会社ソシオネクスト 並直列変換回路、インタフェース回路、及び制御装置
US9543937B2 (en) 2014-09-03 2017-01-10 Microsoft Technology Licensing, Llc Multi-phase clock generation
KR102624454B1 (ko) * 2019-04-05 2024-01-11 에스케이하이닉스 주식회사 데이터 직렬화 회로

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665309A (en) * 1979-10-26 1981-06-03 Sony Corp Time-axis converter
US4445215A (en) * 1982-03-05 1984-04-24 Ampex Corporation Programmable frequency ratio synchronous parallel-to-serial data converter
JPH02105910A (ja) * 1988-10-14 1990-04-18 Hitachi Ltd 論理集積回路
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
US5457718A (en) * 1992-03-02 1995-10-10 International Business Machines Corporation Compact phase recovery scheme using digital circuits
US5349612A (en) * 1992-06-19 1994-09-20 Advanced Micro Devices, Inc. Digital serializer and time delay regulator

Also Published As

Publication number Publication date
US5572721A (en) 1996-11-05
BR9505748A (pt) 1997-12-23
EP0717496A1 (de) 1996-06-19
EP0717496B1 (de) 2000-03-22
DE69515820D1 (de) 2000-04-27
JPH08237142A (ja) 1996-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee