BR9505748A - Circuito para receber um pulso de relógio de entrada - Google Patents

Circuito para receber um pulso de relógio de entrada

Info

Publication number
BR9505748A
BR9505748A BR9505748A BR9505748A BR9505748A BR 9505748 A BR9505748 A BR 9505748A BR 9505748 A BR9505748 A BR 9505748A BR 9505748 A BR9505748 A BR 9505748A BR 9505748 A BR9505748 A BR 9505748A
Authority
BR
Brazil
Prior art keywords
receive
circuit
clock pulse
input clock
input
Prior art date
Application number
BR9505748A
Other languages
English (en)
Inventor
Farhad Rostamian
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Publication of BR9505748A publication Critical patent/BR9505748A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
BR9505748A 1994-12-13 1995-12-12 Circuito para receber um pulso de relógio de entrada BR9505748A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/355,374 US5572721A (en) 1994-12-13 1994-12-13 High speed serial interface between image enhancement logic and ros for implementation of image enhancement algorithms

Publications (1)

Publication Number Publication Date
BR9505748A true BR9505748A (pt) 1997-12-23

Family

ID=23397216

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9505748A BR9505748A (pt) 1994-12-13 1995-12-12 Circuito para receber um pulso de relógio de entrada

Country Status (5)

Country Link
US (1) US5572721A (pt)
EP (1) EP0717496B1 (pt)
JP (1) JPH08237142A (pt)
BR (1) BR9505748A (pt)
DE (1) DE69515820T2 (pt)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768529A (en) * 1995-05-05 1998-06-16 Silicon Graphics, Inc. System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers
US5790166A (en) * 1997-07-17 1998-08-04 Xerox Corporation Modulator for doubling resolution in the fast-scan direction for a laser imager in an electrophotographic printer
US6665360B1 (en) * 1999-12-20 2003-12-16 Cypress Semiconductor Corp. Data transmitter with sequential serialization
JP4412788B2 (ja) * 2000-01-24 2010-02-10 株式会社ルネサステクノロジ パラレル−シリアル変換回路
JP2003317401A (ja) * 2002-04-25 2003-11-07 Sanyo Electric Co Ltd データ記録制御装置
KR100611981B1 (ko) * 2004-05-01 2006-08-11 삼성전자주식회사 이미지의 하프토닝 방법 및 장치
US7161846B2 (en) * 2004-11-16 2007-01-09 Seiko Epson Corporation Dual-edge triggered multiplexer flip-flop and method
US7079055B2 (en) * 2004-11-16 2006-07-18 Seiko Epson Corporation Low-power serializer with half-rate clocking and method
US7489754B2 (en) * 2005-02-08 2009-02-10 Agere Systems Inc. Frequency-lock detector
JP2007096903A (ja) * 2005-09-29 2007-04-12 Rohm Co Ltd パラレルシリアル変換回路およびそれを用いた電子機器
US20080063129A1 (en) * 2006-09-11 2008-03-13 Nokia Corporation System and method for pre-defined wake-up of high speed serial link
JP5471509B2 (ja) * 2010-01-26 2014-04-16 富士通株式会社 パラレル−シリアル変換器
JP2011160369A (ja) * 2010-02-04 2011-08-18 Sony Corp 電子回路、電子機器、デジタル信号処理方法
US8405426B2 (en) 2010-05-28 2013-03-26 Qualcomm Incorporated Method and apparatus to serialize parallel data input values
US8415980B2 (en) 2011-06-28 2013-04-09 Microsoft Corporation Serializing transmitter
US8832487B2 (en) 2011-06-28 2014-09-09 Microsoft Corporation High-speed I/O data system
JP6060637B2 (ja) 2012-11-14 2017-01-18 株式会社ソシオネクスト 並直列変換回路、インタフェース回路、及び制御装置
US9543937B2 (en) 2014-09-03 2017-01-10 Microsoft Technology Licensing, Llc Multi-phase clock generation
KR102624454B1 (ko) * 2019-04-05 2024-01-11 에스케이하이닉스 주식회사 데이터 직렬화 회로

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665309A (en) * 1979-10-26 1981-06-03 Sony Corp Time-axis converter
US4445215A (en) * 1982-03-05 1984-04-24 Ampex Corporation Programmable frequency ratio synchronous parallel-to-serial data converter
JPH02105910A (ja) * 1988-10-14 1990-04-18 Hitachi Ltd 論理集積回路
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
US5457718A (en) * 1992-03-02 1995-10-10 International Business Machines Corporation Compact phase recovery scheme using digital circuits
US5349612A (en) * 1992-06-19 1994-09-20 Advanced Micro Devices, Inc. Digital serializer and time delay regulator

Also Published As

Publication number Publication date
EP0717496A1 (en) 1996-06-19
EP0717496B1 (en) 2000-03-22
JPH08237142A (ja) 1996-09-13
US5572721A (en) 1996-11-05
DE69515820D1 (de) 2000-04-27
DE69515820T2 (de) 2000-07-27

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Legal Events

Date Code Title Description
FB36 Technical and formal requirements: requirement - article 36 of industrial property law
FF Decision: intention to grant
FG9A Patent or certificate of addition granted
B24H Lapse because of non-payment of annual fees (definitively: art 78 iv lpi)
B24F Patent annual fee: publication cancelled

Free format text: ANULADA A PUBLICACAO CODIGO 24.8 NA RPI NO 2258 DE 15/04/2014 POR TER SIDO INDEVIDA.

B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

Free format text: REFERENTE AS 17A, 18A, 19A E 20A ANUIDADES.

B24J Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12)

Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2606 DE 15-12-2020 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.