DE69433965D1 - Verfahren zur Herstellung eines lateralen PNP-Hochfrequenztransistors - Google Patents

Verfahren zur Herstellung eines lateralen PNP-Hochfrequenztransistors

Info

Publication number
DE69433965D1
DE69433965D1 DE69433965T DE69433965T DE69433965D1 DE 69433965 D1 DE69433965 D1 DE 69433965D1 DE 69433965 T DE69433965 T DE 69433965T DE 69433965 T DE69433965 T DE 69433965T DE 69433965 D1 DE69433965 D1 DE 69433965D1
Authority
DE
Germany
Prior art keywords
manufacture
high frequency
pnp transistor
lateral high
frequency pnp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69433965T
Other languages
English (en)
Inventor
Giuseppe Fallico
Raffaele Zambrano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Application granted granted Critical
Publication of DE69433965D1 publication Critical patent/DE69433965D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
DE69433965T 1994-10-26 1994-10-26 Verfahren zur Herstellung eines lateralen PNP-Hochfrequenztransistors Expired - Lifetime DE69433965D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830500A EP0709896B1 (de) 1994-10-26 1994-10-26 Verfahren zur Herstellung eines lateralen PNP-Hochfrequenztransistors

Publications (1)

Publication Number Publication Date
DE69433965D1 true DE69433965D1 (de) 2004-09-30

Family

ID=8218555

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69433965T Expired - Lifetime DE69433965D1 (de) 1994-10-26 1994-10-26 Verfahren zur Herstellung eines lateralen PNP-Hochfrequenztransistors

Country Status (3)

Country Link
US (1) US5796157A (de)
EP (1) EP0709896B1 (de)
DE (1) DE69433965D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69714575D1 (de) * 1997-05-30 2002-09-12 St Microelectronics Srl Laterales PNP-bipolares elektronisches Bauelement und dessen Herstellungsverfahren
EP0881688A1 (de) 1997-05-30 1998-12-02 STMicroelectronics S.r.l. Elektronisches Bauelement vom Typ lateral-bipolar-pnp
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6900105B2 (en) * 2000-03-01 2005-05-31 Freescale Semiconductor, Inc. Semiconductor device and method of manufacture
JP2007180242A (ja) * 2005-12-27 2007-07-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8878344B2 (en) 2012-10-18 2014-11-04 Analog Devices, Inc. Compound semiconductor lateral PNP bipolar transistors
US9502504B2 (en) * 2013-12-19 2016-11-22 International Business Machines Corporation SOI lateral bipolar transistors having surrounding extrinsic base portions

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358870A (ja) * 1986-08-29 1988-03-14 Fujitsu Ltd 半導体装置の製造方法
KR100234550B1 (ko) * 1990-04-02 1999-12-15 클라크 3세 존 엠 증가된 항복 전압을 지닌 트랜지스터 디바이스 및 제조방법
US5187109A (en) * 1991-07-19 1993-02-16 International Business Machines Corporation Lateral bipolar transistor and method of making the same
JPH0793316B2 (ja) * 1992-12-28 1995-10-09 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0709896A1 (de) 1996-05-01
US5796157A (en) 1998-08-18
EP0709896B1 (de) 2004-08-25

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Legal Events

Date Code Title Description
8332 No legal effect for de