DE69433906D1 - Vorrichtung und Verfahren zur Steuerung eines Peripheriebustaktsignals - Google Patents

Vorrichtung und Verfahren zur Steuerung eines Peripheriebustaktsignals

Info

Publication number
DE69433906D1
DE69433906D1 DE69433906T DE69433906T DE69433906D1 DE 69433906 D1 DE69433906 D1 DE 69433906D1 DE 69433906 T DE69433906 T DE 69433906T DE 69433906 T DE69433906 T DE 69433906T DE 69433906 D1 DE69433906 D1 DE 69433906D1
Authority
DE
Germany
Prior art keywords
controlling
clock signal
peripheral bus
bus clock
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69433906T
Other languages
English (en)
Other versions
DE69433906T2 (de
Inventor
Douglas D Gephardt
Kelly M Horton
James R Macdonald
Rita O'brien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/125,406 external-priority patent/US6163848A/en
Priority claimed from US08/131,092 external-priority patent/US5600839A/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69433906D1 publication Critical patent/DE69433906D1/de
Publication of DE69433906T2 publication Critical patent/DE69433906T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
DE69433906T 1993-09-22 1994-09-12 Vorrichtung und Verfahren zur Steuerung eines Peripheriebustaktsignals Expired - Lifetime DE69433906T2 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US125406 1987-11-25
US08/125,406 US6163848A (en) 1993-09-22 1993-09-22 System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus
US131092 1993-10-01
US08/131,092 US5600839A (en) 1993-10-01 1993-10-01 System and method for controlling assertion of a peripheral bus clock signal through a slave device
US23481994A 1994-04-28 1994-04-28
US234819 1994-04-28

Publications (2)

Publication Number Publication Date
DE69433906D1 true DE69433906D1 (de) 2004-08-26
DE69433906T2 DE69433906T2 (de) 2005-07-21

Family

ID=27383240

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69433906T Expired - Lifetime DE69433906T2 (de) 1993-09-22 1994-09-12 Vorrichtung und Verfahren zur Steuerung eines Peripheriebustaktsignals

Country Status (3)

Country Link
EP (1) EP0644475B1 (de)
JP (1) JP3568592B2 (de)
DE (1) DE69433906T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5740454A (en) 1995-12-20 1998-04-14 Compaq Computer Corporation Circuit for setting computer system bus signals to predetermined states in low power mode
DE69827755T2 (de) * 1997-07-21 2005-11-03 Koninklijke Philips Electronics N.V. Verfahren zum betreiben eines kommunikationskanals in einer gemischten master-/slave-teilnehmerumgebung durch eine dynamische schliess- und/oder öffnungsoperation und system zur durchführung des verfahrens
JP3592547B2 (ja) * 1998-09-04 2004-11-24 株式会社ルネサステクノロジ 情報処理装置および信号転送方法
JP4733877B2 (ja) 2001-08-15 2011-07-27 富士通セミコンダクター株式会社 半導体装置
JP3665030B2 (ja) 2002-02-19 2005-06-29 Ｎｅｃマイクロシステム株式会社 バス制御方法及び情報処理装置
US7155618B2 (en) * 2002-03-08 2006-12-26 Freescale Semiconductor, Inc. Low power system and method for a data processing system
US7861192B2 (en) 2007-12-13 2010-12-28 Globalfoundries Inc. Technique to implement clock-gating using a common enable for a plurality of storage cells
US10311191B2 (en) 2017-01-26 2019-06-04 Advanced Micro Devices, Inc. Memory including side-car arrays with irregular sized entries

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381552A (en) * 1978-12-08 1983-04-26 Motorola Inc. Stanby mode controller utilizing microprocessor
JPS59200327A (ja) * 1983-04-26 1984-11-13 Nec Corp 周辺装置の制御方式
JPS62150453A (ja) * 1985-12-23 1987-07-04 Nec Corp マイクロコントロ−ラのスタンバイ制御方式
US5167024A (en) * 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
JP2738229B2 (ja) * 1992-08-03 1998-04-08 日本電気株式会社 シリアル・データ通信制御装置

Also Published As

Publication number Publication date
JPH07152449A (ja) 1995-06-16
EP0644475B1 (de) 2004-07-21
JP3568592B2 (ja) 2004-09-22
EP0644475A2 (de) 1995-03-22
EP0644475A3 (de) 1995-09-27
DE69433906T2 (de) 2005-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY