DE69432639D1 - Flash-eprom-transistoren-matrix und verfahren zur herstellung - Google Patents

Flash-eprom-transistoren-matrix und verfahren zur herstellung

Info

Publication number
DE69432639D1
DE69432639D1 DE69432639T DE69432639T DE69432639D1 DE 69432639 D1 DE69432639 D1 DE 69432639D1 DE 69432639 T DE69432639 T DE 69432639T DE 69432639 T DE69432639 T DE 69432639T DE 69432639 D1 DE69432639 D1 DE 69432639D1
Authority
DE
Germany
Prior art keywords
production method
flash eprom
transistor matrix
eprom transistor
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69432639T
Other languages
English (en)
Other versions
DE69432639T2 (de
Inventor
Fuchia Shone
Dang-Hsing Yiu
Ler Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of DE69432639D1 publication Critical patent/DE69432639D1/de
Application granted granted Critical
Publication of DE69432639T2 publication Critical patent/DE69432639T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69432639T 1994-09-13 1994-09-13 Flash-eprom-transistoren-matrix und verfahren zur herstellung Expired - Lifetime DE69432639T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1994/010276 WO1996008840A1 (en) 1994-09-13 1994-09-13 A flash eprom transistor array and method for manufacturing the same

Publications (2)

Publication Number Publication Date
DE69432639D1 true DE69432639D1 (de) 2003-06-12
DE69432639T2 DE69432639T2 (de) 2004-04-08

Family

ID=22242966

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69432639T Expired - Lifetime DE69432639T2 (de) 1994-09-13 1994-09-13 Flash-eprom-transistoren-matrix und verfahren zur herstellung

Country Status (4)

Country Link
EP (1) EP0728367B1 (de)
JP (1) JPH09505945A (de)
DE (1) DE69432639T2 (de)
WO (1) WO1996008840A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0782148B1 (de) 1995-12-29 2003-02-26 STMicroelectronics S.r.l. Verfahren zum Verhindern von Störungen während des Programmierens und des Löschens eines nichtflüchtigen Speichers
EP1017097A1 (de) 1998-12-29 2000-07-05 STMicroelectronics S.r.l. Herstellungsverfahren von selbstjustierten Silizidkontakten für Halbleiterfestwertspeicher
US6682978B1 (en) 1999-08-30 2004-01-27 Advanced Micro Devices, Inc. Integrated circuit having increased gate coupling capacitance
US6576949B1 (en) 1999-08-30 2003-06-10 Advanced Micro Devices, Inc. Integrated circuit having optimized gate coupling capacitance
FR2799050A1 (fr) * 1999-09-24 2001-03-30 St Microelectronics Sa Procede de fabrication de points memoire eprom a surface reduite
US6232635B1 (en) * 2000-04-06 2001-05-15 Advanced Micro Devices, Inc. Method to fabricate a high coupling flash cell with less silicide seam problem
EP1170798B1 (de) * 2000-07-04 2006-09-06 STMicroelectronics S.r.l. Architektur eines Festwertspeicherfelds
IT1318145B1 (it) * 2000-07-11 2003-07-23 St Microelectronics Srl Processo per fabbricare una cella di memoria non-volatile con unaregione di gate flottante autoallineata all'isolamento e con un alto
JP2003007869A (ja) * 2001-06-26 2003-01-10 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0712063B2 (ja) * 1987-10-21 1995-02-08 三菱電機株式会社 不揮発性半導体記憶装置
FR2635409B1 (fr) * 1988-08-11 1991-08-02 Sgs Thomson Microelectronics Memoire de type eprom a haute densite d'integration possedant un facteur de couplage eleve, et son procede de fabrication
US5051795A (en) * 1989-11-21 1991-09-24 Texas Instruments Incorporated EEPROM with trench-isolated bitlines
US4994403A (en) * 1989-12-28 1991-02-19 Texas Instruments Incorporated Method of making an electrically programmable, electrically erasable memory array cell
US5060195A (en) * 1989-12-29 1991-10-22 Texas Instruments Incorporated Hot electron programmable, tunnel electron erasable contactless EEPROM
US5021848A (en) * 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5019879A (en) * 1990-03-15 1991-05-28 Chiu Te Long Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
EP1032034A1 (de) * 1992-01-22 2000-08-30 Macronix International Co., Ltd. Verfahren zur Speicherbauelementherstellung

Also Published As

Publication number Publication date
WO1996008840A1 (en) 1996-03-21
EP0728367A4 (de) 1997-08-20
JPH09505945A (ja) 1997-06-10
EP0728367B1 (de) 2003-05-07
DE69432639T2 (de) 2004-04-08
EP0728367A1 (de) 1996-08-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition